Module stm32h7::stm32h743::pwr::cr2

This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.

Structs

BRENR	Value of the field
BRRDYR	Value of the field
MONENR	Value of the field
R	Value read from the register
TEMPHR	Value of the field
TEMPLR	Value of the field
VBATHR	Value of the field
VBATLR	Value of the field
W	Value to write to the register
_BRENW	Proxy
_MONENW	Proxy