#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CR1 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `IOLOCK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IOLOCKR {
#[doc = "IO configuration unlocked"]
UNLOCKED,
#[doc = "IO configuration locked"]
LOCKED,
}
impl IOLOCKR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
IOLOCKR::UNLOCKED => false,
IOLOCKR::LOCKED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> IOLOCKR {
match value {
false => IOLOCKR::UNLOCKED,
true => IOLOCKR::LOCKED,
}
}
#[doc = "Checks if the value of the field is `UNLOCKED`"]
#[inline(always)]
pub fn is_unlocked(&self) -> bool {
*self == IOLOCKR::UNLOCKED
}
#[doc = "Checks if the value of the field is `LOCKED`"]
#[inline(always)]
pub fn is_locked(&self) -> bool {
*self == IOLOCKR::LOCKED
}
}
#[doc = "Possible values of the field `TCRCINI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCRCINIR {
#[doc = "All zeros TX CRC initialization pattern"]
ALLZEROS,
#[doc = "All ones TX CRC initialization pattern"]
ALLONES,
}
impl TCRCINIR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
TCRCINIR::ALLZEROS => false,
TCRCINIR::ALLONES => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> TCRCINIR {
match value {
false => TCRCINIR::ALLZEROS,
true => TCRCINIR::ALLONES,
}
}
#[doc = "Checks if the value of the field is `ALLZEROS`"]
#[inline(always)]
pub fn is_all_zeros(&self) -> bool {
*self == TCRCINIR::ALLZEROS
}
#[doc = "Checks if the value of the field is `ALLONES`"]
#[inline(always)]
pub fn is_all_ones(&self) -> bool {
*self == TCRCINIR::ALLONES
}
}
#[doc = "Values that can be written to the field `TCRCINI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TCRCINIW {
#[doc = "All zeros TX CRC initialization pattern"]
ALLZEROS,
#[doc = "All ones TX CRC initialization pattern"]
ALLONES,
}
impl TCRCINIW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
TCRCINIW::ALLZEROS => false,
TCRCINIW::ALLONES => true,
}
}
}
#[doc = r"Proxy"]
pub struct _TCRCINIW<'a> {
w: &'a mut W,
}
impl<'a> _TCRCINIW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TCRCINIW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "All zeros TX CRC initialization pattern"]
#[inline(always)]
pub fn all_zeros(self) -> &'a mut W {
self.variant(TCRCINIW::ALLZEROS)
}
#[doc = "All ones TX CRC initialization pattern"]
#[inline(always)]
pub fn all_ones(self) -> &'a mut W {
self.variant(TCRCINIW::ALLONES)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = "Possible values of the field `RCRCINI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RCRCINIR {
#[doc = "All zeros RX CRC initialization pattern"]
ALLZEROS,
#[doc = "All ones RX CRC initialization pattern"]
ALLONES,
}
impl RCRCINIR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
RCRCINIR::ALLZEROS => false,
RCRCINIR::ALLONES => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> RCRCINIR {
match value {
false => RCRCINIR::ALLZEROS,
true => RCRCINIR::ALLONES,
}
}
#[doc = "Checks if the value of the field is `ALLZEROS`"]
#[inline(always)]
pub fn is_all_zeros(&self) -> bool {
*self == RCRCINIR::ALLZEROS
}
#[doc = "Checks if the value of the field is `ALLONES`"]
#[inline(always)]
pub fn is_all_ones(&self) -> bool {
*self == RCRCINIR::ALLONES
}
}
#[doc = "Values that can be written to the field `RCRCINI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RCRCINIW {
#[doc = "All zeros RX CRC initialization pattern"]
ALLZEROS,
#[doc = "All ones RX CRC initialization pattern"]
ALLONES,
}
impl RCRCINIW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
RCRCINIW::ALLZEROS => false,
RCRCINIW::ALLONES => true,
}
}
}
#[doc = r"Proxy"]
pub struct _RCRCINIW<'a> {
w: &'a mut W,
}
impl<'a> _RCRCINIW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RCRCINIW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "All zeros RX CRC initialization pattern"]
#[inline(always)]
pub fn all_zeros(self) -> &'a mut W {
self.variant(RCRCINIW::ALLZEROS)
}
#[doc = "All ones RX CRC initialization pattern"]
#[inline(always)]
pub fn all_ones(self) -> &'a mut W {
self.variant(RCRCINIW::ALLONES)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 14);
self.w.bits |= ((value as u32) & 0x01) << 14;
self.w
}
}
#[doc = "Possible values of the field `CRC33_17`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRC33_17R {
#[doc = "Full size (33/17 bit) CRC polynomial is not used"]
DISABLED,
#[doc = "Full size (33/17 bit) CRC polynomial is used"]
ENABLED,
}
impl CRC33_17R {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CRC33_17R::DISABLED => false,
CRC33_17R::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CRC33_17R {
match value {
false => CRC33_17R::DISABLED,
true => CRC33_17R::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CRC33_17R::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CRC33_17R::ENABLED
}
}
#[doc = "Values that can be written to the field `CRC33_17`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CRC33_17W {
#[doc = "Full size (33/17 bit) CRC polynomial is not used"]
DISABLED,
#[doc = "Full size (33/17 bit) CRC polynomial is used"]
ENABLED,
}
impl CRC33_17W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CRC33_17W::DISABLED => false,
CRC33_17W::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CRC33_17W<'a> {
w: &'a mut W,
}
impl<'a> _CRC33_17W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CRC33_17W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Full size (33/17 bit) CRC polynomial is not used"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(CRC33_17W::DISABLED)
}
#[doc = "Full size (33/17 bit) CRC polynomial is used"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(CRC33_17W::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 13);
self.w.bits |= ((value as u32) & 0x01) << 13;
self.w
}
}
#[doc = "Possible values of the field `SSI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSIR {
#[doc = "0 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
SLAVESELECTED,
#[doc = "1 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
SLAVENOTSELECTED,
}
impl SSIR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SSIR::SLAVESELECTED => false,
SSIR::SLAVENOTSELECTED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SSIR {
match value {
false => SSIR::SLAVESELECTED,
true => SSIR::SLAVENOTSELECTED,
}
}
#[doc = "Checks if the value of the field is `SLAVESELECTED`"]
#[inline(always)]
pub fn is_slave_selected(&self) -> bool {
*self == SSIR::SLAVESELECTED
}
#[doc = "Checks if the value of the field is `SLAVENOTSELECTED`"]
#[inline(always)]
pub fn is_slave_not_selected(&self) -> bool {
*self == SSIR::SLAVENOTSELECTED
}
}
#[doc = "Values that can be written to the field `SSI`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSIW {
#[doc = "0 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
SLAVESELECTED,
#[doc = "1 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
SLAVENOTSELECTED,
}
impl SSIW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SSIW::SLAVESELECTED => false,
SSIW::SLAVENOTSELECTED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SSIW<'a> {
w: &'a mut W,
}
impl<'a> _SSIW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SSIW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "0 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
#[inline(always)]
pub fn slave_selected(self) -> &'a mut W {
self.variant(SSIW::SLAVESELECTED)
}
#[doc = "1 is forced onto the SS signal and the I/O value of the SS pin is ignored"]
#[inline(always)]
pub fn slave_not_selected(self) -> &'a mut W {
self.variant(SSIW::SLAVENOTSELECTED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 12);
self.w.bits |= ((value as u32) & 0x01) << 12;
self.w
}
}
#[doc = "Possible values of the field `HDDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HDDIRR {
#[doc = "Receiver in half duplex mode"]
RECEIVER,
#[doc = "Transmitter in half duplex mode"]
TRANSMITTER,
}
impl HDDIRR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
HDDIRR::RECEIVER => false,
HDDIRR::TRANSMITTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> HDDIRR {
match value {
false => HDDIRR::RECEIVER,
true => HDDIRR::TRANSMITTER,
}
}
#[doc = "Checks if the value of the field is `RECEIVER`"]
#[inline(always)]
pub fn is_receiver(&self) -> bool {
*self == HDDIRR::RECEIVER
}
#[doc = "Checks if the value of the field is `TRANSMITTER`"]
#[inline(always)]
pub fn is_transmitter(&self) -> bool {
*self == HDDIRR::TRANSMITTER
}
}
#[doc = "Values that can be written to the field `HDDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HDDIRW {
#[doc = "Receiver in half duplex mode"]
RECEIVER,
#[doc = "Transmitter in half duplex mode"]
TRANSMITTER,
}
impl HDDIRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
HDDIRW::RECEIVER => false,
HDDIRW::TRANSMITTER => true,
}
}
}
#[doc = r"Proxy"]
pub struct _HDDIRW<'a> {
w: &'a mut W,
}
impl<'a> _HDDIRW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: HDDIRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Receiver in half duplex mode"]
#[inline(always)]
pub fn receiver(self) -> &'a mut W {
self.variant(HDDIRW::RECEIVER)
}
#[doc = "Transmitter in half duplex mode"]
#[inline(always)]
pub fn transmitter(self) -> &'a mut W {
self.variant(HDDIRW::TRANSMITTER)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 11);
self.w.bits |= ((value as u32) & 0x01) << 11;
self.w
}
}
#[doc = "Values that can be written to the field `CSUSP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CSUSPW {
#[doc = "Do not request master suspend"]
NOTREQUESTED,
#[doc = "Request master suspend"]
REQUESTED,
}
impl CSUSPW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CSUSPW::NOTREQUESTED => false,
CSUSPW::REQUESTED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CSUSPW<'a> {
w: &'a mut W,
}
impl<'a> _CSUSPW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CSUSPW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Do not request master suspend"]
#[inline(always)]
pub fn not_requested(self) -> &'a mut W {
self.variant(CSUSPW::NOTREQUESTED)
}
#[doc = "Request master suspend"]
#[inline(always)]
pub fn requested(self) -> &'a mut W {
self.variant(CSUSPW::REQUESTED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 10);
self.w.bits |= ((value as u32) & 0x01) << 10;
self.w
}
}
#[doc = "Possible values of the field `CSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CSTARTR {
#[doc = "Do not start master transfer"]
NOTSTARTED,
#[doc = "Start master transfer"]
STARTED,
}
impl CSTARTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CSTARTR::NOTSTARTED => false,
CSTARTR::STARTED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CSTARTR {
match value {
false => CSTARTR::NOTSTARTED,
true => CSTARTR::STARTED,
}
}
#[doc = "Checks if the value of the field is `NOTSTARTED`"]
#[inline(always)]
pub fn is_not_started(&self) -> bool {
*self == CSTARTR::NOTSTARTED
}
#[doc = "Checks if the value of the field is `STARTED`"]
#[inline(always)]
pub fn is_started(&self) -> bool {
*self == CSTARTR::STARTED
}
}
#[doc = "Values that can be written to the field `CSTART`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CSTARTW {
#[doc = "Do not start master transfer"]
NOTSTARTED,
#[doc = "Start master transfer"]
STARTED,
}
impl CSTARTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CSTARTW::NOTSTARTED => false,
CSTARTW::STARTED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CSTARTW<'a> {
w: &'a mut W,
}
impl<'a> _CSTARTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CSTARTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Do not start master transfer"]
#[inline(always)]
pub fn not_started(self) -> &'a mut W {
self.variant(CSTARTW::NOTSTARTED)
}
#[doc = "Start master transfer"]
#[inline(always)]
pub fn started(self) -> &'a mut W {
self.variant(CSTARTW::STARTED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 9);
self.w.bits |= ((value as u32) & 0x01) << 9;
self.w
}
}
#[doc = "Possible values of the field `MASRX`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MASRXR {
#[doc = "Automatic suspend in master receive-only mode disabled"]
DISABLED,
#[doc = "Automatic suspend in master receive-only mode enabled"]
ENABLED,
}
impl MASRXR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
MASRXR::DISABLED => false,
MASRXR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> MASRXR {
match value {
false => MASRXR::DISABLED,
true => MASRXR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MASRXR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MASRXR::ENABLED
}
}
#[doc = "Values that can be written to the field `MASRX`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MASRXW {
#[doc = "Automatic suspend in master receive-only mode disabled"]
DISABLED,
#[doc = "Automatic suspend in master receive-only mode enabled"]
ENABLED,
}
impl MASRXW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
MASRXW::DISABLED => false,
MASRXW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _MASRXW<'a> {
w: &'a mut W,
}
impl<'a> _MASRXW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MASRXW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Automatic suspend in master receive-only mode disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(MASRXW::DISABLED)
}
#[doc = "Automatic suspend in master receive-only mode enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(MASRXW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `SPE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPER {
#[doc = "Peripheral disabled"]
DISABLED,
#[doc = "Peripheral enabled"]
ENABLED,
}
impl SPER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SPER::DISABLED => false,
SPER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SPER {
match value {
false => SPER::DISABLED,
true => SPER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SPER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SPER::ENABLED
}
}
#[doc = "Values that can be written to the field `SPE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPEW {
#[doc = "Peripheral disabled"]
DISABLED,
#[doc = "Peripheral enabled"]
ENABLED,
}
impl SPEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SPEW::DISABLED => false,
SPEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SPEW<'a> {
w: &'a mut W,
}
impl<'a> _SPEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Peripheral disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SPEW::DISABLED)
}
#[doc = "Peripheral enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SPEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 0);
self.w.bits |= ((value as u32) & 0x01) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 16 - Locking the AF configuration of associated IOs"]
#[inline(always)]
pub fn iolock(&self) -> IOLOCKR {
IOLOCKR::_from(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 15 - CRC calculation initialization pattern control for transmitter"]
#[inline(always)]
pub fn tcrcini(&self) -> TCRCINIR {
TCRCINIR::_from(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 14 - CRC calculation initialization pattern control for receiver"]
#[inline(always)]
pub fn rcrcini(&self) -> RCRCINIR {
RCRCINIR::_from(((self.bits >> 14) & 0x01) != 0)
}
#[doc = "Bit 13 - 32-bit CRC polynomial configuration"]
#[inline(always)]
pub fn crc33_17(&self) -> CRC33_17R {
CRC33_17R::_from(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 12 - Internal SS signal input level"]
#[inline(always)]
pub fn ssi(&self) -> SSIR {
SSIR::_from(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 11 - Rx/Tx direction at Half-duplex mode"]
#[inline(always)]
pub fn hddir(&self) -> HDDIRR {
HDDIRR::_from(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 9 - Master transfer start"]
#[inline(always)]
pub fn cstart(&self) -> CSTARTR {
CSTARTR::_from(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 8 - Master automatic SUSP in Receive mode"]
#[inline(always)]
pub fn masrx(&self) -> MASRXR {
MASRXR::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 0 - Serial Peripheral Enable"]
#[inline(always)]
pub fn spe(&self) -> SPER {
SPER::_from(((self.bits >> 0) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 15 - CRC calculation initialization pattern control for transmitter"]
#[inline(always)]
pub fn tcrcini(&mut self) -> _TCRCINIW {
_TCRCINIW { w: self }
}
#[doc = "Bit 14 - CRC calculation initialization pattern control for receiver"]
#[inline(always)]
pub fn rcrcini(&mut self) -> _RCRCINIW {
_RCRCINIW { w: self }
}
#[doc = "Bit 13 - 32-bit CRC polynomial configuration"]
#[inline(always)]
pub fn crc33_17(&mut self) -> _CRC33_17W {
_CRC33_17W { w: self }
}
#[doc = "Bit 12 - Internal SS signal input level"]
#[inline(always)]
pub fn ssi(&mut self) -> _SSIW {
_SSIW { w: self }
}
#[doc = "Bit 11 - Rx/Tx direction at Half-duplex mode"]
#[inline(always)]
pub fn hddir(&mut self) -> _HDDIRW {
_HDDIRW { w: self }
}
#[doc = "Bit 10 - Master SUSPend request"]
#[inline(always)]
pub fn csusp(&mut self) -> _CSUSPW {
_CSUSPW { w: self }
}
#[doc = "Bit 9 - Master transfer start"]
#[inline(always)]
pub fn cstart(&mut self) -> _CSTARTW {
_CSTARTW { w: self }
}
#[doc = "Bit 8 - Master automatic SUSP in Receive mode"]
#[inline(always)]
pub fn masrx(&mut self) -> _MASRXW {
_MASRXW { w: self }
}
#[doc = "Bit 0 - Serial Peripheral Enable"]
#[inline(always)]
pub fn spe(&mut self) -> _SPEW {
_SPEW { w: self }
}
}