#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCMR1_INPUT {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = r"Value of the field"]
pub struct IC2FR {
bits: u8,
}
impl IC2FR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _IC2FW<'a> {
w: &'a mut W,
}
impl<'a> _IC2FW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 12);
self.w.bits |= ((value as u32) & 0x0f) << 12;
self.w
}
}
#[doc = r"Value of the field"]
pub struct IC2PSCR {
bits: u8,
}
impl IC2PSCR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _IC2PSCW<'a> {
w: &'a mut W,
}
impl<'a> _IC2PSCW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 10);
self.w.bits |= ((value as u32) & 0x03) << 10;
self.w
}
}
#[doc = "Possible values of the field `CC2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC2SR {
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
TI2,
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
TI1,
#[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
TRC,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CC2SR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CC2SR::TI2 => 0x01,
CC2SR::TI1 => 0x02,
CC2SR::TRC => 0x03,
CC2SR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CC2SR {
match value {
1 => CC2SR::TI2,
2 => CC2SR::TI1,
3 => CC2SR::TRC,
i => CC2SR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `TI2`"]
#[inline(always)]
pub fn is_ti2(&self) -> bool {
*self == CC2SR::TI2
}
#[doc = "Checks if the value of the field is `TI1`"]
#[inline(always)]
pub fn is_ti1(&self) -> bool {
*self == CC2SR::TI1
}
#[doc = "Checks if the value of the field is `TRC`"]
#[inline(always)]
pub fn is_trc(&self) -> bool {
*self == CC2SR::TRC
}
}
#[doc = "Values that can be written to the field `CC2S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC2SW {
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
TI2,
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
TI1,
#[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
TRC,
}
impl CC2SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CC2SW::TI2 => 1,
CC2SW::TI1 => 2,
CC2SW::TRC => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _CC2SW<'a> {
w: &'a mut W,
}
impl<'a> _CC2SW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CC2SW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI2"]
#[inline(always)]
pub fn ti2(self) -> &'a mut W {
self.variant(CC2SW::TI2)
}
#[doc = "CC2 channel is configured as input, IC2 is mapped on TI1"]
#[inline(always)]
pub fn ti1(self) -> &'a mut W {
self.variant(CC2SW::TI1)
}
#[doc = "CC2 channel is configured as input, IC2 is mapped on TRC"]
#[inline(always)]
pub fn trc(self) -> &'a mut W {
self.variant(CC2SW::TRC)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 8);
self.w.bits |= ((value as u32) & 0x03) << 8;
self.w
}
}
#[doc = "Possible values of the field `IC1F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IC1FR {
#[doc = "No filter, sampling is done at fDTS"]
NOFILTER,
#[doc = "fSAMPLING=fCK_INT, N=2"]
FCK_INT_N2,
#[doc = "fSAMPLING=fCK_INT, N=4"]
FCK_INT_N4,
#[doc = "fSAMPLING=fCK_INT, N=8"]
FCK_INT_N8,
#[doc = "fSAMPLING=fDTS/2, N=6"]
FDTS_DIV2_N6,
#[doc = "fSAMPLING=fDTS/2, N=8"]
FDTS_DIV2_N8,
#[doc = "fSAMPLING=fDTS/4, N=6"]
FDTS_DIV4_N6,
#[doc = "fSAMPLING=fDTS/4, N=8"]
FDTS_DIV4_N8,
#[doc = "fSAMPLING=fDTS/8, N=6"]
FDTS_DIV8_N6,
#[doc = "fSAMPLING=fDTS/8, N=8"]
FDTS_DIV8_N8,
#[doc = "fSAMPLING=fDTS/16, N=5"]
FDTS_DIV16_N5,
#[doc = "fSAMPLING=fDTS/16, N=6"]
FDTS_DIV16_N6,
#[doc = "fSAMPLING=fDTS/16, N=8"]
FDTS_DIV16_N8,
#[doc = "fSAMPLING=fDTS/32, N=5"]
FDTS_DIV32_N5,
#[doc = "fSAMPLING=fDTS/32, N=6"]
FDTS_DIV32_N6,
#[doc = "fSAMPLING=fDTS/32, N=8"]
FDTS_DIV32_N8,
}
impl IC1FR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
IC1FR::NOFILTER => 0,
IC1FR::FCK_INT_N2 => 0x01,
IC1FR::FCK_INT_N4 => 0x02,
IC1FR::FCK_INT_N8 => 0x03,
IC1FR::FDTS_DIV2_N6 => 0x04,
IC1FR::FDTS_DIV2_N8 => 0x05,
IC1FR::FDTS_DIV4_N6 => 0x06,
IC1FR::FDTS_DIV4_N8 => 0x07,
IC1FR::FDTS_DIV8_N6 => 0x08,
IC1FR::FDTS_DIV8_N8 => 0x09,
IC1FR::FDTS_DIV16_N5 => 0x0a,
IC1FR::FDTS_DIV16_N6 => 0x0b,
IC1FR::FDTS_DIV16_N8 => 0x0c,
IC1FR::FDTS_DIV32_N5 => 0x0d,
IC1FR::FDTS_DIV32_N6 => 0x0e,
IC1FR::FDTS_DIV32_N8 => 0x0f,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> IC1FR {
match value {
0 => IC1FR::NOFILTER,
1 => IC1FR::FCK_INT_N2,
2 => IC1FR::FCK_INT_N4,
3 => IC1FR::FCK_INT_N8,
4 => IC1FR::FDTS_DIV2_N6,
5 => IC1FR::FDTS_DIV2_N8,
6 => IC1FR::FDTS_DIV4_N6,
7 => IC1FR::FDTS_DIV4_N8,
8 => IC1FR::FDTS_DIV8_N6,
9 => IC1FR::FDTS_DIV8_N8,
10 => IC1FR::FDTS_DIV16_N5,
11 => IC1FR::FDTS_DIV16_N6,
12 => IC1FR::FDTS_DIV16_N8,
13 => IC1FR::FDTS_DIV32_N5,
14 => IC1FR::FDTS_DIV32_N6,
15 => IC1FR::FDTS_DIV32_N8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `NOFILTER`"]
#[inline(always)]
pub fn is_no_filter(&self) -> bool {
*self == IC1FR::NOFILTER
}
#[doc = "Checks if the value of the field is `FCK_INT_N2`"]
#[inline(always)]
pub fn is_fck_int_n2(&self) -> bool {
*self == IC1FR::FCK_INT_N2
}
#[doc = "Checks if the value of the field is `FCK_INT_N4`"]
#[inline(always)]
pub fn is_fck_int_n4(&self) -> bool {
*self == IC1FR::FCK_INT_N4
}
#[doc = "Checks if the value of the field is `FCK_INT_N8`"]
#[inline(always)]
pub fn is_fck_int_n8(&self) -> bool {
*self == IC1FR::FCK_INT_N8
}
#[doc = "Checks if the value of the field is `FDTS_DIV2_N6`"]
#[inline(always)]
pub fn is_fdts_div2_n6(&self) -> bool {
*self == IC1FR::FDTS_DIV2_N6
}
#[doc = "Checks if the value of the field is `FDTS_DIV2_N8`"]
#[inline(always)]
pub fn is_fdts_div2_n8(&self) -> bool {
*self == IC1FR::FDTS_DIV2_N8
}
#[doc = "Checks if the value of the field is `FDTS_DIV4_N6`"]
#[inline(always)]
pub fn is_fdts_div4_n6(&self) -> bool {
*self == IC1FR::FDTS_DIV4_N6
}
#[doc = "Checks if the value of the field is `FDTS_DIV4_N8`"]
#[inline(always)]
pub fn is_fdts_div4_n8(&self) -> bool {
*self == IC1FR::FDTS_DIV4_N8
}
#[doc = "Checks if the value of the field is `FDTS_DIV8_N6`"]
#[inline(always)]
pub fn is_fdts_div8_n6(&self) -> bool {
*self == IC1FR::FDTS_DIV8_N6
}
#[doc = "Checks if the value of the field is `FDTS_DIV8_N8`"]
#[inline(always)]
pub fn is_fdts_div8_n8(&self) -> bool {
*self == IC1FR::FDTS_DIV8_N8
}
#[doc = "Checks if the value of the field is `FDTS_DIV16_N5`"]
#[inline(always)]
pub fn is_fdts_div16_n5(&self) -> bool {
*self == IC1FR::FDTS_DIV16_N5
}
#[doc = "Checks if the value of the field is `FDTS_DIV16_N6`"]
#[inline(always)]
pub fn is_fdts_div16_n6(&self) -> bool {
*self == IC1FR::FDTS_DIV16_N6
}
#[doc = "Checks if the value of the field is `FDTS_DIV16_N8`"]
#[inline(always)]
pub fn is_fdts_div16_n8(&self) -> bool {
*self == IC1FR::FDTS_DIV16_N8
}
#[doc = "Checks if the value of the field is `FDTS_DIV32_N5`"]
#[inline(always)]
pub fn is_fdts_div32_n5(&self) -> bool {
*self == IC1FR::FDTS_DIV32_N5
}
#[doc = "Checks if the value of the field is `FDTS_DIV32_N6`"]
#[inline(always)]
pub fn is_fdts_div32_n6(&self) -> bool {
*self == IC1FR::FDTS_DIV32_N6
}
#[doc = "Checks if the value of the field is `FDTS_DIV32_N8`"]
#[inline(always)]
pub fn is_fdts_div32_n8(&self) -> bool {
*self == IC1FR::FDTS_DIV32_N8
}
}
#[doc = "Values that can be written to the field `IC1F`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IC1FW {
#[doc = "No filter, sampling is done at fDTS"]
NOFILTER,
#[doc = "fSAMPLING=fCK_INT, N=2"]
FCK_INT_N2,
#[doc = "fSAMPLING=fCK_INT, N=4"]
FCK_INT_N4,
#[doc = "fSAMPLING=fCK_INT, N=8"]
FCK_INT_N8,
#[doc = "fSAMPLING=fDTS/2, N=6"]
FDTS_DIV2_N6,
#[doc = "fSAMPLING=fDTS/2, N=8"]
FDTS_DIV2_N8,
#[doc = "fSAMPLING=fDTS/4, N=6"]
FDTS_DIV4_N6,
#[doc = "fSAMPLING=fDTS/4, N=8"]
FDTS_DIV4_N8,
#[doc = "fSAMPLING=fDTS/8, N=6"]
FDTS_DIV8_N6,
#[doc = "fSAMPLING=fDTS/8, N=8"]
FDTS_DIV8_N8,
#[doc = "fSAMPLING=fDTS/16, N=5"]
FDTS_DIV16_N5,
#[doc = "fSAMPLING=fDTS/16, N=6"]
FDTS_DIV16_N6,
#[doc = "fSAMPLING=fDTS/16, N=8"]
FDTS_DIV16_N8,
#[doc = "fSAMPLING=fDTS/32, N=5"]
FDTS_DIV32_N5,
#[doc = "fSAMPLING=fDTS/32, N=6"]
FDTS_DIV32_N6,
#[doc = "fSAMPLING=fDTS/32, N=8"]
FDTS_DIV32_N8,
}
impl IC1FW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
IC1FW::NOFILTER => 0,
IC1FW::FCK_INT_N2 => 1,
IC1FW::FCK_INT_N4 => 2,
IC1FW::FCK_INT_N8 => 3,
IC1FW::FDTS_DIV2_N6 => 4,
IC1FW::FDTS_DIV2_N8 => 5,
IC1FW::FDTS_DIV4_N6 => 6,
IC1FW::FDTS_DIV4_N8 => 7,
IC1FW::FDTS_DIV8_N6 => 8,
IC1FW::FDTS_DIV8_N8 => 9,
IC1FW::FDTS_DIV16_N5 => 10,
IC1FW::FDTS_DIV16_N6 => 11,
IC1FW::FDTS_DIV16_N8 => 12,
IC1FW::FDTS_DIV32_N5 => 13,
IC1FW::FDTS_DIV32_N6 => 14,
IC1FW::FDTS_DIV32_N8 => 15,
}
}
}
#[doc = r"Proxy"]
pub struct _IC1FW<'a> {
w: &'a mut W,
}
impl<'a> _IC1FW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: IC1FW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "No filter, sampling is done at fDTS"]
#[inline(always)]
pub fn no_filter(self) -> &'a mut W {
self.variant(IC1FW::NOFILTER)
}
#[doc = "fSAMPLING=fCK_INT, N=2"]
#[inline(always)]
pub fn fck_int_n2(self) -> &'a mut W {
self.variant(IC1FW::FCK_INT_N2)
}
#[doc = "fSAMPLING=fCK_INT, N=4"]
#[inline(always)]
pub fn fck_int_n4(self) -> &'a mut W {
self.variant(IC1FW::FCK_INT_N4)
}
#[doc = "fSAMPLING=fCK_INT, N=8"]
#[inline(always)]
pub fn fck_int_n8(self) -> &'a mut W {
self.variant(IC1FW::FCK_INT_N8)
}
#[doc = "fSAMPLING=fDTS/2, N=6"]
#[inline(always)]
pub fn fdts_div2_n6(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV2_N6)
}
#[doc = "fSAMPLING=fDTS/2, N=8"]
#[inline(always)]
pub fn fdts_div2_n8(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV2_N8)
}
#[doc = "fSAMPLING=fDTS/4, N=6"]
#[inline(always)]
pub fn fdts_div4_n6(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV4_N6)
}
#[doc = "fSAMPLING=fDTS/4, N=8"]
#[inline(always)]
pub fn fdts_div4_n8(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV4_N8)
}
#[doc = "fSAMPLING=fDTS/8, N=6"]
#[inline(always)]
pub fn fdts_div8_n6(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV8_N6)
}
#[doc = "fSAMPLING=fDTS/8, N=8"]
#[inline(always)]
pub fn fdts_div8_n8(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV8_N8)
}
#[doc = "fSAMPLING=fDTS/16, N=5"]
#[inline(always)]
pub fn fdts_div16_n5(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV16_N5)
}
#[doc = "fSAMPLING=fDTS/16, N=6"]
#[inline(always)]
pub fn fdts_div16_n6(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV16_N6)
}
#[doc = "fSAMPLING=fDTS/16, N=8"]
#[inline(always)]
pub fn fdts_div16_n8(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV16_N8)
}
#[doc = "fSAMPLING=fDTS/32, N=5"]
#[inline(always)]
pub fn fdts_div32_n5(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV32_N5)
}
#[doc = "fSAMPLING=fDTS/32, N=6"]
#[inline(always)]
pub fn fdts_div32_n6(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV32_N6)
}
#[doc = "fSAMPLING=fDTS/32, N=8"]
#[inline(always)]
pub fn fdts_div32_n8(self) -> &'a mut W {
self.variant(IC1FW::FDTS_DIV32_N8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 4);
self.w.bits |= ((value as u32) & 0x0f) << 4;
self.w
}
}
#[doc = r"Value of the field"]
pub struct IC1PSCR {
bits: u8,
}
impl IC1PSCR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _IC1PSCW<'a> {
w: &'a mut W,
}
impl<'a> _IC1PSCW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 2);
self.w.bits |= ((value as u32) & 0x03) << 2;
self.w
}
}
#[doc = "Possible values of the field `CC1S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC1SR {
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
TI1,
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
TI2,
#[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
TRC,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CC1SR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CC1SR::TI1 => 0x01,
CC1SR::TI2 => 0x02,
CC1SR::TRC => 0x03,
CC1SR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CC1SR {
match value {
1 => CC1SR::TI1,
2 => CC1SR::TI2,
3 => CC1SR::TRC,
i => CC1SR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `TI1`"]
#[inline(always)]
pub fn is_ti1(&self) -> bool {
*self == CC1SR::TI1
}
#[doc = "Checks if the value of the field is `TI2`"]
#[inline(always)]
pub fn is_ti2(&self) -> bool {
*self == CC1SR::TI2
}
#[doc = "Checks if the value of the field is `TRC`"]
#[inline(always)]
pub fn is_trc(&self) -> bool {
*self == CC1SR::TRC
}
}
#[doc = "Values that can be written to the field `CC1S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC1SW {
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
TI1,
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
TI2,
#[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
TRC,
}
impl CC1SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CC1SW::TI1 => 1,
CC1SW::TI2 => 2,
CC1SW::TRC => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _CC1SW<'a> {
w: &'a mut W,
}
impl<'a> _CC1SW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CC1SW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI1"]
#[inline(always)]
pub fn ti1(self) -> &'a mut W {
self.variant(CC1SW::TI1)
}
#[doc = "CC1 channel is configured as input, IC1 is mapped on TI2"]
#[inline(always)]
pub fn ti2(self) -> &'a mut W {
self.variant(CC1SW::TI2)
}
#[doc = "CC1 channel is configured as input, IC1 is mapped on TRC"]
#[inline(always)]
pub fn trc(self) -> &'a mut W {
self.variant(CC1SW::TRC)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 0);
self.w.bits |= ((value as u32) & 0x03) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 12:15 - Input capture 2 filter"]
#[inline(always)]
pub fn ic2f(&self) -> IC2FR {
let bits = ((self.bits >> 12) & 0x0f) as u8;
IC2FR { bits }
}
#[doc = "Bits 10:11 - Input capture 2 prescaler"]
#[inline(always)]
pub fn ic2psc(&self) -> IC2PSCR {
let bits = ((self.bits >> 10) & 0x03) as u8;
IC2PSCR { bits }
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&self) -> CC2SR {
CC2SR::_from(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 4:7 - Input capture 1 filter"]
#[inline(always)]
pub fn ic1f(&self) -> IC1FR {
IC1FR::_from(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 2:3 - Input capture 1 prescaler"]
#[inline(always)]
pub fn ic1psc(&self) -> IC1PSCR {
let bits = ((self.bits >> 2) & 0x03) as u8;
IC1PSCR { bits }
}
#[doc = "Bits 0:1 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&self) -> CC1SR {
CC1SR::_from(((self.bits >> 0) & 0x03) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 12:15 - Input capture 2 filter"]
#[inline(always)]
pub fn ic2f(&mut self) -> _IC2FW {
_IC2FW { w: self }
}
#[doc = "Bits 10:11 - Input capture 2 prescaler"]
#[inline(always)]
pub fn ic2psc(&mut self) -> _IC2PSCW {
_IC2PSCW { w: self }
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&mut self) -> _CC2SW {
_CC2SW { w: self }
}
#[doc = "Bits 4:7 - Input capture 1 filter"]
#[inline(always)]
pub fn ic1f(&mut self) -> _IC1FW {
_IC1FW { w: self }
}
#[doc = "Bits 2:3 - Input capture 1 prescaler"]
#[inline(always)]
pub fn ic1psc(&mut self) -> _IC1PSCW {
_IC1PSCW { w: self }
}
#[doc = "Bits 0:1 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&mut self) -> _CC1SW {
_CC1SW { w: self }
}
}