#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCMR2_OUTPUT {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `CC3S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC3SR {
#[doc = "CC3 channel is configured as output"]
OUTPUT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CC3SR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CC3SR::OUTPUT => 0,
CC3SR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CC3SR {
match value {
0 => CC3SR::OUTPUT,
i => CC3SR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `OUTPUT`"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == CC3SR::OUTPUT
}
}
#[doc = "Values that can be written to the field `CC3S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC3SW {
#[doc = "CC3 channel is configured as output"]
OUTPUT,
}
impl CC3SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CC3SW::OUTPUT => 0,
}
}
}
#[doc = r"Proxy"]
pub struct _CC3SW<'a> {
w: &'a mut W,
}
impl<'a> _CC3SW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CC3SW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "CC3 channel is configured as output"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CC3SW::OUTPUT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 0);
self.w.bits |= ((value as u32) & 0x03) << 0;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC3FER {
bits: bool,
}
impl OC3FER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC3FEW<'a> {
w: &'a mut W,
}
impl<'a> _OC3FEW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 2);
self.w.bits |= ((value as u32) & 0x01) << 2;
self.w
}
}
#[doc = "Possible values of the field `OC3PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC3PER {
#[doc = "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"]
DISABLED,
#[doc = "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"]
ENABLED,
}
impl OC3PER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
OC3PER::DISABLED => false,
OC3PER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> OC3PER {
match value {
false => OC3PER::DISABLED,
true => OC3PER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OC3PER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OC3PER::ENABLED
}
}
#[doc = "Values that can be written to the field `OC3PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC3PEW {
#[doc = "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"]
DISABLED,
#[doc = "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"]
ENABLED,
}
impl OC3PEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
OC3PEW::DISABLED => false,
OC3PEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _OC3PEW<'a> {
w: &'a mut W,
}
impl<'a> _OC3PEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC3PEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(OC3PEW::DISABLED)
}
#[doc = "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(OC3PEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 3);
self.w.bits |= ((value as u32) & 0x01) << 3;
self.w
}
}
#[doc = "Possible values of the field `OC3M`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC3MR {
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
FROZEN,
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
ACTIVEONMATCH,
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
INACTIVEONMATCH,
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
TOGGLE,
#[doc = "OCyREF is forced low"]
FORCEINACTIVE,
#[doc = "OCyREF is forced high"]
FORCEACTIVE,
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
PWMMODE1,
#[doc = "Inversely to PwmMode1"]
PWMMODE2,
#[doc = "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
OPMMODE1,
#[doc = "Inversely to OpmMode1"]
OPMMODE2,
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
COMBINEDPWMMODE1,
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
COMBINEDPWMMODE2,
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
ASYMMETRICPWMMODE1,
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
ASYMMETRICPWMMODE2,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl OC3MR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
OC3MR::FROZEN => 0,
OC3MR::ACTIVEONMATCH => 0x01,
OC3MR::INACTIVEONMATCH => 0x02,
OC3MR::TOGGLE => 0x03,
OC3MR::FORCEINACTIVE => 0x04,
OC3MR::FORCEACTIVE => 0x05,
OC3MR::PWMMODE1 => 0x06,
OC3MR::PWMMODE2 => 0x07,
OC3MR::OPMMODE1 => 0x08,
OC3MR::OPMMODE2 => 0x09,
OC3MR::COMBINEDPWMMODE1 => 0x0c,
OC3MR::COMBINEDPWMMODE2 => 0x0d,
OC3MR::ASYMMETRICPWMMODE1 => 0x0e,
OC3MR::ASYMMETRICPWMMODE2 => 0x0f,
OC3MR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> OC3MR {
match value {
0 => OC3MR::FROZEN,
1 => OC3MR::ACTIVEONMATCH,
2 => OC3MR::INACTIVEONMATCH,
3 => OC3MR::TOGGLE,
4 => OC3MR::FORCEINACTIVE,
5 => OC3MR::FORCEACTIVE,
6 => OC3MR::PWMMODE1,
7 => OC3MR::PWMMODE2,
8 => OC3MR::OPMMODE1,
9 => OC3MR::OPMMODE2,
12 => OC3MR::COMBINEDPWMMODE1,
13 => OC3MR::COMBINEDPWMMODE2,
14 => OC3MR::ASYMMETRICPWMMODE1,
15 => OC3MR::ASYMMETRICPWMMODE2,
i => OC3MR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `FROZEN`"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == OC3MR::FROZEN
}
#[doc = "Checks if the value of the field is `ACTIVEONMATCH`"]
#[inline(always)]
pub fn is_active_on_match(&self) -> bool {
*self == OC3MR::ACTIVEONMATCH
}
#[doc = "Checks if the value of the field is `INACTIVEONMATCH`"]
#[inline(always)]
pub fn is_inactive_on_match(&self) -> bool {
*self == OC3MR::INACTIVEONMATCH
}
#[doc = "Checks if the value of the field is `TOGGLE`"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == OC3MR::TOGGLE
}
#[doc = "Checks if the value of the field is `FORCEINACTIVE`"]
#[inline(always)]
pub fn is_force_inactive(&self) -> bool {
*self == OC3MR::FORCEINACTIVE
}
#[doc = "Checks if the value of the field is `FORCEACTIVE`"]
#[inline(always)]
pub fn is_force_active(&self) -> bool {
*self == OC3MR::FORCEACTIVE
}
#[doc = "Checks if the value of the field is `PWMMODE1`"]
#[inline(always)]
pub fn is_pwm_mode1(&self) -> bool {
*self == OC3MR::PWMMODE1
}
#[doc = "Checks if the value of the field is `PWMMODE2`"]
#[inline(always)]
pub fn is_pwm_mode2(&self) -> bool {
*self == OC3MR::PWMMODE2
}
#[doc = "Checks if the value of the field is `OPMMODE1`"]
#[inline(always)]
pub fn is_opm_mode1(&self) -> bool {
*self == OC3MR::OPMMODE1
}
#[doc = "Checks if the value of the field is `OPMMODE2`"]
#[inline(always)]
pub fn is_opm_mode2(&self) -> bool {
*self == OC3MR::OPMMODE2
}
#[doc = "Checks if the value of the field is `COMBINEDPWMMODE1`"]
#[inline(always)]
pub fn is_combined_pwm_mode1(&self) -> bool {
*self == OC3MR::COMBINEDPWMMODE1
}
#[doc = "Checks if the value of the field is `COMBINEDPWMMODE2`"]
#[inline(always)]
pub fn is_combined_pwm_mode2(&self) -> bool {
*self == OC3MR::COMBINEDPWMMODE2
}
#[doc = "Checks if the value of the field is `ASYMMETRICPWMMODE1`"]
#[inline(always)]
pub fn is_asymmetric_pwm_mode1(&self) -> bool {
*self == OC3MR::ASYMMETRICPWMMODE1
}
#[doc = "Checks if the value of the field is `ASYMMETRICPWMMODE2`"]
#[inline(always)]
pub fn is_asymmetric_pwm_mode2(&self) -> bool {
*self == OC3MR::ASYMMETRICPWMMODE2
}
}
#[doc = "Values that can be written to the field `OC3M`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC3MW {
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
FROZEN,
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
ACTIVEONMATCH,
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
INACTIVEONMATCH,
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
TOGGLE,
#[doc = "OCyREF is forced low"]
FORCEINACTIVE,
#[doc = "OCyREF is forced high"]
FORCEACTIVE,
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
PWMMODE1,
#[doc = "Inversely to PwmMode1"]
PWMMODE2,
#[doc = "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
OPMMODE1,
#[doc = "Inversely to OpmMode1"]
OPMMODE2,
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
COMBINEDPWMMODE1,
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
COMBINEDPWMMODE2,
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
ASYMMETRICPWMMODE1,
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
ASYMMETRICPWMMODE2,
}
impl OC3MW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
OC3MW::FROZEN => 0,
OC3MW::ACTIVEONMATCH => 1,
OC3MW::INACTIVEONMATCH => 2,
OC3MW::TOGGLE => 3,
OC3MW::FORCEINACTIVE => 4,
OC3MW::FORCEACTIVE => 5,
OC3MW::PWMMODE1 => 6,
OC3MW::PWMMODE2 => 7,
OC3MW::OPMMODE1 => 8,
OC3MW::OPMMODE2 => 9,
OC3MW::COMBINEDPWMMODE1 => 12,
OC3MW::COMBINEDPWMMODE2 => 13,
OC3MW::ASYMMETRICPWMMODE1 => 14,
OC3MW::ASYMMETRICPWMMODE2 => 15,
}
}
}
#[doc = r"Proxy"]
pub struct _OC3MW<'a> {
w: &'a mut W,
}
impl<'a> _OC3MW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC3MW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
#[inline(always)]
pub fn frozen(self) -> &'a mut W {
self.variant(OC3MW::FROZEN)
}
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
#[inline(always)]
pub fn active_on_match(self) -> &'a mut W {
self.variant(OC3MW::ACTIVEONMATCH)
}
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
#[inline(always)]
pub fn inactive_on_match(self) -> &'a mut W {
self.variant(OC3MW::INACTIVEONMATCH)
}
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
#[inline(always)]
pub fn toggle(self) -> &'a mut W {
self.variant(OC3MW::TOGGLE)
}
#[doc = "OCyREF is forced low"]
#[inline(always)]
pub fn force_inactive(self) -> &'a mut W {
self.variant(OC3MW::FORCEINACTIVE)
}
#[doc = "OCyREF is forced high"]
#[inline(always)]
pub fn force_active(self) -> &'a mut W {
self.variant(OC3MW::FORCEACTIVE)
}
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
#[inline(always)]
pub fn pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::PWMMODE1)
}
#[doc = "Inversely to PwmMode1"]
#[inline(always)]
pub fn pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::PWMMODE2)
}
#[doc = "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
#[inline(always)]
pub fn opm_mode1(self) -> &'a mut W {
self.variant(OC3MW::OPMMODE1)
}
#[doc = "Inversely to OpmMode1"]
#[inline(always)]
pub fn opm_mode2(self) -> &'a mut W {
self.variant(OC3MW::OPMMODE2)
}
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
#[inline(always)]
pub fn combined_pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::COMBINEDPWMMODE1)
}
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
#[inline(always)]
pub fn combined_pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::COMBINEDPWMMODE2)
}
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn asymmetric_pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::ASYMMETRICPWMMODE1)
}
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn asymmetric_pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::ASYMMETRICPWMMODE2)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 4);
self.w.bits |= ((value as u32) & 0x07) << 4;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC3CER {
bits: bool,
}
impl OC3CER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC3CEW<'a> {
w: &'a mut W,
}
impl<'a> _OC3CEW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 7);
self.w.bits |= ((value as u32) & 0x01) << 7;
self.w
}
}
#[doc = "Possible values of the field `CC4S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC4SR {
#[doc = "CC4 channel is configured as output"]
OUTPUT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CC4SR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CC4SR::OUTPUT => 0,
CC4SR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CC4SR {
match value {
0 => CC4SR::OUTPUT,
i => CC4SR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `OUTPUT`"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == CC4SR::OUTPUT
}
}
#[doc = "Values that can be written to the field `CC4S`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CC4SW {
#[doc = "CC4 channel is configured as output"]
OUTPUT,
}
impl CC4SW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CC4SW::OUTPUT => 0,
}
}
}
#[doc = r"Proxy"]
pub struct _CC4SW<'a> {
w: &'a mut W,
}
impl<'a> _CC4SW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CC4SW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "CC4 channel is configured as output"]
#[inline(always)]
pub fn output(self) -> &'a mut W {
self.variant(CC4SW::OUTPUT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 8);
self.w.bits |= ((value as u32) & 0x03) << 8;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC4FER {
bits: bool,
}
impl OC4FER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC4FEW<'a> {
w: &'a mut W,
}
impl<'a> _OC4FEW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 10);
self.w.bits |= ((value as u32) & 0x01) << 10;
self.w
}
}
#[doc = "Possible values of the field `OC4PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC4PER {
#[doc = "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"]
DISABLED,
#[doc = "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"]
ENABLED,
}
impl OC4PER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
OC4PER::DISABLED => false,
OC4PER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> OC4PER {
match value {
false => OC4PER::DISABLED,
true => OC4PER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OC4PER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OC4PER::ENABLED
}
}
#[doc = "Values that can be written to the field `OC4PE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC4PEW {
#[doc = "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"]
DISABLED,
#[doc = "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"]
ENABLED,
}
impl OC4PEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
OC4PEW::DISABLED => false,
OC4PEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _OC4PEW<'a> {
w: &'a mut W,
}
impl<'a> _OC4PEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC4PEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(OC4PEW::DISABLED)
}
#[doc = "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(OC4PEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 11);
self.w.bits |= ((value as u32) & 0x01) << 11;
self.w
}
}
#[doc = "Possible values of the field `OC4M`"]
pub type OC4MR = OC3MR;
#[doc = "Values that can be written to the field `OC4M`"]
pub type OC4MW = OC3MW;
#[doc = r"Proxy"]
pub struct _OC4MW<'a> {
w: &'a mut W,
}
impl<'a> _OC4MW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC4MW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
#[inline(always)]
pub fn frozen(self) -> &'a mut W {
self.variant(OC3MW::FROZEN)
}
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
#[inline(always)]
pub fn active_on_match(self) -> &'a mut W {
self.variant(OC3MW::ACTIVEONMATCH)
}
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
#[inline(always)]
pub fn inactive_on_match(self) -> &'a mut W {
self.variant(OC3MW::INACTIVEONMATCH)
}
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
#[inline(always)]
pub fn toggle(self) -> &'a mut W {
self.variant(OC3MW::TOGGLE)
}
#[doc = "OCyREF is forced low"]
#[inline(always)]
pub fn force_inactive(self) -> &'a mut W {
self.variant(OC3MW::FORCEINACTIVE)
}
#[doc = "OCyREF is forced high"]
#[inline(always)]
pub fn force_active(self) -> &'a mut W {
self.variant(OC3MW::FORCEACTIVE)
}
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
#[inline(always)]
pub fn pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::PWMMODE1)
}
#[doc = "Inversely to PwmMode1"]
#[inline(always)]
pub fn pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::PWMMODE2)
}
#[doc = "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
#[inline(always)]
pub fn opm_mode1(self) -> &'a mut W {
self.variant(OC3MW::OPMMODE1)
}
#[doc = "Inversely to OpmMode1"]
#[inline(always)]
pub fn opm_mode2(self) -> &'a mut W {
self.variant(OC3MW::OPMMODE2)
}
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
#[inline(always)]
pub fn combined_pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::COMBINEDPWMMODE1)
}
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
#[inline(always)]
pub fn combined_pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::COMBINEDPWMMODE2)
}
#[doc = "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn asymmetric_pwm_mode1(self) -> &'a mut W {
self.variant(OC3MW::ASYMMETRICPWMMODE1)
}
#[doc = "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn asymmetric_pwm_mode2(self) -> &'a mut W {
self.variant(OC3MW::ASYMMETRICPWMMODE2)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 12);
self.w.bits |= ((value as u32) & 0x07) << 12;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC4CER {
bits: bool,
}
impl OC4CER {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC4CEW<'a> {
w: &'a mut W,
}
impl<'a> _OC4CEW<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC3M_3R {
bits: bool,
}
impl OC3M_3R {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC3M_3W<'a> {
w: &'a mut W,
}
impl<'a> _OC3M_3W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = r"Value of the field"]
pub struct OC4M_4R {
bits: bool,
}
impl OC4M_4R {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r"Proxy"]
pub struct _OC4M_4W<'a> {
w: &'a mut W,
}
impl<'a> _OC4M_4W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&self) -> CC3SR {
CC3SR::_from(((self.bits >> 0) & 0x03) as u8)
}
#[doc = "Bit 2 - Output compare 3 fast enable"]
#[inline(always)]
pub fn oc3fe(&self) -> OC3FER {
let bits = ((self.bits >> 2) & 0x01) != 0;
OC3FER { bits }
}
#[doc = "Bit 3 - Output compare 3 preload enable"]
#[inline(always)]
pub fn oc3pe(&self) -> OC3PER {
OC3PER::_from(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bits 4:6 - Output compare 3 mode"]
#[inline(always)]
pub fn oc3m(&self) -> OC3MR {
OC3MR::_from(((self.bits >> 4) & 0x07) as u8)
}
#[doc = "Bit 7 - Output compare 3 clear enable"]
#[inline(always)]
pub fn oc3ce(&self) -> OC3CER {
let bits = ((self.bits >> 7) & 0x01) != 0;
OC3CER { bits }
}
#[doc = "Bits 8:9 - Capture/Compare 4 selection"]
#[inline(always)]
pub fn cc4s(&self) -> CC4SR {
CC4SR::_from(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bit 10 - Output compare 4 fast enable"]
#[inline(always)]
pub fn oc4fe(&self) -> OC4FER {
let bits = ((self.bits >> 10) & 0x01) != 0;
OC4FER { bits }
}
#[doc = "Bit 11 - Output compare 4 preload enable"]
#[inline(always)]
pub fn oc4pe(&self) -> OC4PER {
OC4PER::_from(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bits 12:14 - Output compare 4 mode"]
#[inline(always)]
pub fn oc4m(&self) -> OC4MR {
OC4MR::_from(((self.bits >> 12) & 0x07) as u8)
}
#[doc = "Bit 15 - Output compare 4 clear enable"]
#[inline(always)]
pub fn oc4ce(&self) -> OC4CER {
let bits = ((self.bits >> 15) & 0x01) != 0;
OC4CER { bits }
}
#[doc = "Bit 16 - Output Compare 3 mode - bit 3"]
#[inline(always)]
pub fn oc3m_3(&self) -> OC3M_3R {
let bits = ((self.bits >> 16) & 0x01) != 0;
OC3M_3R { bits }
}
#[doc = "Bit 24 - Output Compare 4 mode - bit 3"]
#[inline(always)]
pub fn oc4m_4(&self) -> OC4M_4R {
let bits = ((self.bits >> 24) & 0x01) != 0;
OC4M_4R { bits }
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&mut self) -> _CC3SW {
_CC3SW { w: self }
}
#[doc = "Bit 2 - Output compare 3 fast enable"]
#[inline(always)]
pub fn oc3fe(&mut self) -> _OC3FEW {
_OC3FEW { w: self }
}
#[doc = "Bit 3 - Output compare 3 preload enable"]
#[inline(always)]
pub fn oc3pe(&mut self) -> _OC3PEW {
_OC3PEW { w: self }
}
#[doc = "Bits 4:6 - Output compare 3 mode"]
#[inline(always)]
pub fn oc3m(&mut self) -> _OC3MW {
_OC3MW { w: self }
}
#[doc = "Bit 7 - Output compare 3 clear enable"]
#[inline(always)]
pub fn oc3ce(&mut self) -> _OC3CEW {
_OC3CEW { w: self }
}
#[doc = "Bits 8:9 - Capture/Compare 4 selection"]
#[inline(always)]
pub fn cc4s(&mut self) -> _CC4SW {
_CC4SW { w: self }
}
#[doc = "Bit 10 - Output compare 4 fast enable"]
#[inline(always)]
pub fn oc4fe(&mut self) -> _OC4FEW {
_OC4FEW { w: self }
}
#[doc = "Bit 11 - Output compare 4 preload enable"]
#[inline(always)]
pub fn oc4pe(&mut self) -> _OC4PEW {
_OC4PEW { w: self }
}
#[doc = "Bits 12:14 - Output compare 4 mode"]
#[inline(always)]
pub fn oc4m(&mut self) -> _OC4MW {
_OC4MW { w: self }
}
#[doc = "Bit 15 - Output compare 4 clear enable"]
#[inline(always)]
pub fn oc4ce(&mut self) -> _OC4CEW {
_OC4CEW { w: self }
}
#[doc = "Bit 16 - Output Compare 3 mode - bit 3"]
#[inline(always)]
pub fn oc3m_3(&mut self) -> _OC3M_3W {
_OC3M_3W { w: self }
}
#[doc = "Bit 24 - Output Compare 4 mode - bit 3"]
#[inline(always)]
pub fn oc4m_4(&mut self) -> _OC4M_4W {
_OC4M_4W { w: self }
}
}