#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG2 {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `AFCNTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AFCNTRR {
#[doc = "Peripheral takes no control of GPIOs while disabled"]
NOTCONTROLLED,
#[doc = "Peripheral controls GPIOs while disabled"]
CONTROLLED,
}
impl AFCNTRR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
AFCNTRR::NOTCONTROLLED => false,
AFCNTRR::CONTROLLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> AFCNTRR {
match value {
false => AFCNTRR::NOTCONTROLLED,
true => AFCNTRR::CONTROLLED,
}
}
#[doc = "Checks if the value of the field is `NOTCONTROLLED`"]
#[inline(always)]
pub fn is_not_controlled(&self) -> bool {
*self == AFCNTRR::NOTCONTROLLED
}
#[doc = "Checks if the value of the field is `CONTROLLED`"]
#[inline(always)]
pub fn is_controlled(&self) -> bool {
*self == AFCNTRR::CONTROLLED
}
}
#[doc = "Values that can be written to the field `AFCNTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AFCNTRW {
#[doc = "Peripheral takes no control of GPIOs while disabled"]
NOTCONTROLLED,
#[doc = "Peripheral controls GPIOs while disabled"]
CONTROLLED,
}
impl AFCNTRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
AFCNTRW::NOTCONTROLLED => false,
AFCNTRW::CONTROLLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _AFCNTRW<'a> {
w: &'a mut W,
}
impl<'a> _AFCNTRW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: AFCNTRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Peripheral takes no control of GPIOs while disabled"]
#[inline(always)]
pub fn not_controlled(self) -> &'a mut W {
self.variant(AFCNTRW::NOTCONTROLLED)
}
#[doc = "Peripheral controls GPIOs while disabled"]
#[inline(always)]
pub fn controlled(self) -> &'a mut W {
self.variant(AFCNTRW::CONTROLLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 31);
self.w.bits |= ((value as u32) & 0x01) << 31;
self.w
}
}
#[doc = "Possible values of the field `SSOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSOMR {
#[doc = "SS is asserted until data transfer complete"]
ASSERTED,
#[doc = "Data frames interleaved with SS not asserted during MIDI"]
NOTASSERTED,
}
impl SSOMR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SSOMR::ASSERTED => false,
SSOMR::NOTASSERTED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SSOMR {
match value {
false => SSOMR::ASSERTED,
true => SSOMR::NOTASSERTED,
}
}
#[doc = "Checks if the value of the field is `ASSERTED`"]
#[inline(always)]
pub fn is_asserted(&self) -> bool {
*self == SSOMR::ASSERTED
}
#[doc = "Checks if the value of the field is `NOTASSERTED`"]
#[inline(always)]
pub fn is_not_asserted(&self) -> bool {
*self == SSOMR::NOTASSERTED
}
}
#[doc = "Values that can be written to the field `SSOM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSOMW {
#[doc = "SS is asserted until data transfer complete"]
ASSERTED,
#[doc = "Data frames interleaved with SS not asserted during MIDI"]
NOTASSERTED,
}
impl SSOMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SSOMW::ASSERTED => false,
SSOMW::NOTASSERTED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SSOMW<'a> {
w: &'a mut W,
}
impl<'a> _SSOMW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SSOMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SS is asserted until data transfer complete"]
#[inline(always)]
pub fn asserted(self) -> &'a mut W {
self.variant(SSOMW::ASSERTED)
}
#[doc = "Data frames interleaved with SS not asserted during MIDI"]
#[inline(always)]
pub fn not_asserted(self) -> &'a mut W {
self.variant(SSOMW::NOTASSERTED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 30);
self.w.bits |= ((value as u32) & 0x01) << 30;
self.w
}
}
#[doc = "Possible values of the field `SSOE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSOER {
#[doc = "SS output is disabled in master mode"]
DISABLED,
#[doc = "SS output is enabled in master mode"]
ENABLED,
}
impl SSOER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SSOER::DISABLED => false,
SSOER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SSOER {
match value {
false => SSOER::DISABLED,
true => SSOER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SSOER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SSOER::ENABLED
}
}
#[doc = "Values that can be written to the field `SSOE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSOEW {
#[doc = "SS output is disabled in master mode"]
DISABLED,
#[doc = "SS output is enabled in master mode"]
ENABLED,
}
impl SSOEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SSOEW::DISABLED => false,
SSOEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SSOEW<'a> {
w: &'a mut W,
}
impl<'a> _SSOEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SSOEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SS output is disabled in master mode"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SSOEW::DISABLED)
}
#[doc = "SS output is enabled in master mode"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SSOEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 29);
self.w.bits |= ((value as u32) & 0x01) << 29;
self.w
}
}
#[doc = "Possible values of the field `SSIOP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSIOPR {
#[doc = "Low level is active for SS signal"]
ACTIVELOW,
#[doc = "High level is active for SS signal"]
ACTIVEHIGH,
}
impl SSIOPR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SSIOPR::ACTIVELOW => false,
SSIOPR::ACTIVEHIGH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SSIOPR {
match value {
false => SSIOPR::ACTIVELOW,
true => SSIOPR::ACTIVEHIGH,
}
}
#[doc = "Checks if the value of the field is `ACTIVELOW`"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == SSIOPR::ACTIVELOW
}
#[doc = "Checks if the value of the field is `ACTIVEHIGH`"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == SSIOPR::ACTIVEHIGH
}
}
#[doc = "Values that can be written to the field `SSIOP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSIOPW {
#[doc = "Low level is active for SS signal"]
ACTIVELOW,
#[doc = "High level is active for SS signal"]
ACTIVEHIGH,
}
impl SSIOPW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SSIOPW::ACTIVELOW => false,
SSIOPW::ACTIVEHIGH => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SSIOPW<'a> {
w: &'a mut W,
}
impl<'a> _SSIOPW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SSIOPW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Low level is active for SS signal"]
#[inline(always)]
pub fn active_low(self) -> &'a mut W {
self.variant(SSIOPW::ACTIVELOW)
}
#[doc = "High level is active for SS signal"]
#[inline(always)]
pub fn active_high(self) -> &'a mut W {
self.variant(SSIOPW::ACTIVEHIGH)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 28);
self.w.bits |= ((value as u32) & 0x01) << 28;
self.w
}
}
#[doc = "Possible values of the field `SSM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSMR {
#[doc = "Software slave management disabled"]
DISABLED,
#[doc = "Software slave management enabled"]
ENABLED,
}
impl SSMR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
SSMR::DISABLED => false,
SSMR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> SSMR {
match value {
false => SSMR::DISABLED,
true => SSMR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SSMR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SSMR::ENABLED
}
}
#[doc = "Values that can be written to the field `SSM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSMW {
#[doc = "Software slave management disabled"]
DISABLED,
#[doc = "Software slave management enabled"]
ENABLED,
}
impl SSMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
SSMW::DISABLED => false,
SSMW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _SSMW<'a> {
w: &'a mut W,
}
impl<'a> _SSMW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SSMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Software slave management disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SSMW::DISABLED)
}
#[doc = "Software slave management enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SSMW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 26);
self.w.bits |= ((value as u32) & 0x01) << 26;
self.w
}
}
#[doc = "Possible values of the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLR {
#[doc = "CK to 0 when idle"]
IDLELOW,
#[doc = "CK to 1 when idle"]
IDLEHIGH,
}
impl CPOLR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CPOLR::IDLELOW => false,
CPOLR::IDLEHIGH => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CPOLR {
match value {
false => CPOLR::IDLELOW,
true => CPOLR::IDLEHIGH,
}
}
#[doc = "Checks if the value of the field is `IDLELOW`"]
#[inline(always)]
pub fn is_idle_low(&self) -> bool {
*self == CPOLR::IDLELOW
}
#[doc = "Checks if the value of the field is `IDLEHIGH`"]
#[inline(always)]
pub fn is_idle_high(&self) -> bool {
*self == CPOLR::IDLEHIGH
}
}
#[doc = "Values that can be written to the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLW {
#[doc = "CK to 0 when idle"]
IDLELOW,
#[doc = "CK to 1 when idle"]
IDLEHIGH,
}
impl CPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CPOLW::IDLELOW => false,
CPOLW::IDLEHIGH => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "CK to 0 when idle"]
#[inline(always)]
pub fn idle_low(self) -> &'a mut W {
self.variant(CPOLW::IDLELOW)
}
#[doc = "CK to 1 when idle"]
#[inline(always)]
pub fn idle_high(self) -> &'a mut W {
self.variant(CPOLW::IDLEHIGH)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 25);
self.w.bits |= ((value as u32) & 0x01) << 25;
self.w
}
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPHAR {
#[doc = "The first clock transition is the first data capture edge"]
FIRSTEDGE,
#[doc = "The second clock transition is the first data capture edge"]
SECONDEDGE,
}
impl CPHAR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CPHAR::FIRSTEDGE => false,
CPHAR::SECONDEDGE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CPHAR {
match value {
false => CPHAR::FIRSTEDGE,
true => CPHAR::SECONDEDGE,
}
}
#[doc = "Checks if the value of the field is `FIRSTEDGE`"]
#[inline(always)]
pub fn is_first_edge(&self) -> bool {
*self == CPHAR::FIRSTEDGE
}
#[doc = "Checks if the value of the field is `SECONDEDGE`"]
#[inline(always)]
pub fn is_second_edge(&self) -> bool {
*self == CPHAR::SECONDEDGE
}
}
#[doc = "Values that can be written to the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPHAW {
#[doc = "The first clock transition is the first data capture edge"]
FIRSTEDGE,
#[doc = "The second clock transition is the first data capture edge"]
SECONDEDGE,
}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CPHAW::FIRSTEDGE => false,
CPHAW::SECONDEDGE => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CPHAW<'a> {
w: &'a mut W,
}
impl<'a> _CPHAW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CPHAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The first clock transition is the first data capture edge"]
#[inline(always)]
pub fn first_edge(self) -> &'a mut W {
self.variant(CPHAW::FIRSTEDGE)
}
#[doc = "The second clock transition is the first data capture edge"]
#[inline(always)]
pub fn second_edge(self) -> &'a mut W {
self.variant(CPHAW::SECONDEDGE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
#[doc = "Possible values of the field `LSBFRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LSBFRSTR {
#[doc = "Data is transmitted/received with the MSB first"]
MSBFIRST,
#[doc = "Data is transmitted/received with the LSB first"]
LSBFIRST,
}
impl LSBFRSTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
LSBFRSTR::MSBFIRST => false,
LSBFRSTR::LSBFIRST => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> LSBFRSTR {
match value {
false => LSBFRSTR::MSBFIRST,
true => LSBFRSTR::LSBFIRST,
}
}
#[doc = "Checks if the value of the field is `MSBFIRST`"]
#[inline(always)]
pub fn is_msbfirst(&self) -> bool {
*self == LSBFRSTR::MSBFIRST
}
#[doc = "Checks if the value of the field is `LSBFIRST`"]
#[inline(always)]
pub fn is_lsbfirst(&self) -> bool {
*self == LSBFRSTR::LSBFIRST
}
}
#[doc = "Values that can be written to the field `LSBFRST`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LSBFRSTW {
#[doc = "Data is transmitted/received with the MSB first"]
MSBFIRST,
#[doc = "Data is transmitted/received with the LSB first"]
LSBFIRST,
}
impl LSBFRSTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
LSBFRSTW::MSBFIRST => false,
LSBFRSTW::LSBFIRST => true,
}
}
}
#[doc = r"Proxy"]
pub struct _LSBFRSTW<'a> {
w: &'a mut W,
}
impl<'a> _LSBFRSTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: LSBFRSTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Data is transmitted/received with the MSB first"]
#[inline(always)]
pub fn msbfirst(self) -> &'a mut W {
self.variant(LSBFRSTW::MSBFIRST)
}
#[doc = "Data is transmitted/received with the LSB first"]
#[inline(always)]
pub fn lsbfirst(self) -> &'a mut W {
self.variant(LSBFRSTW::LSBFIRST)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 23);
self.w.bits |= ((value as u32) & 0x01) << 23;
self.w
}
}
#[doc = "Possible values of the field `MASTER`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MASTERR {
#[doc = "Slave configuration"]
SLAVE,
#[doc = "Master configuration"]
MASTER,
}
impl MASTERR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
MASTERR::SLAVE => false,
MASTERR::MASTER => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> MASTERR {
match value {
false => MASTERR::SLAVE,
true => MASTERR::MASTER,
}
}
#[doc = "Checks if the value of the field is `SLAVE`"]
#[inline(always)]
pub fn is_slave(&self) -> bool {
*self == MASTERR::SLAVE
}
#[doc = "Checks if the value of the field is `MASTER`"]
#[inline(always)]
pub fn is_master(&self) -> bool {
*self == MASTERR::MASTER
}
}
#[doc = "Values that can be written to the field `MASTER`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MASTERW {
#[doc = "Slave configuration"]
SLAVE,
#[doc = "Master configuration"]
MASTER,
}
impl MASTERW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
MASTERW::SLAVE => false,
MASTERW::MASTER => true,
}
}
}
#[doc = r"Proxy"]
pub struct _MASTERW<'a> {
w: &'a mut W,
}
impl<'a> _MASTERW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MASTERW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Slave configuration"]
#[inline(always)]
pub fn slave(self) -> &'a mut W {
self.variant(MASTERW::SLAVE)
}
#[doc = "Master configuration"]
#[inline(always)]
pub fn master(self) -> &'a mut W {
self.variant(MASTERW::MASTER)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = "Possible values of the field `SP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPR {
#[doc = "Motorola SPI protocol"]
MOTOROLA,
#[doc = "TI SPI protocol"]
TI,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SPR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SPR::MOTOROLA => 0,
SPR::TI => 0x01,
SPR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SPR {
match value {
0 => SPR::MOTOROLA,
1 => SPR::TI,
i => SPR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `MOTOROLA`"]
#[inline(always)]
pub fn is_motorola(&self) -> bool {
*self == SPR::MOTOROLA
}
#[doc = "Checks if the value of the field is `TI`"]
#[inline(always)]
pub fn is_ti(&self) -> bool {
*self == SPR::TI
}
}
#[doc = "Values that can be written to the field `SP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPW {
#[doc = "Motorola SPI protocol"]
MOTOROLA,
#[doc = "TI SPI protocol"]
TI,
}
impl SPW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SPW::MOTOROLA => 0,
SPW::TI => 1,
}
}
}
#[doc = r"Proxy"]
pub struct _SPW<'a> {
w: &'a mut W,
}
impl<'a> _SPW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Motorola SPI protocol"]
#[inline(always)]
pub fn motorola(self) -> &'a mut W {
self.variant(SPW::MOTOROLA)
}
#[doc = "TI SPI protocol"]
#[inline(always)]
pub fn ti(self) -> &'a mut W {
self.variant(SPW::TI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 19);
self.w.bits |= ((value as u32) & 0x07) << 19;
self.w
}
}
#[doc = "Possible values of the field `COMM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMMR {
#[doc = "Full duplex"]
FULLDUPLEX,
#[doc = "Simplex transmitter only"]
TRANSMITTER,
#[doc = "Simplex receiver only"]
RECEIVER,
#[doc = "Half duplex"]
HALFDUPLEX,
}
impl COMMR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
COMMR::FULLDUPLEX => 0,
COMMR::TRANSMITTER => 0x01,
COMMR::RECEIVER => 0x02,
COMMR::HALFDUPLEX => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> COMMR {
match value {
0 => COMMR::FULLDUPLEX,
1 => COMMR::TRANSMITTER,
2 => COMMR::RECEIVER,
3 => COMMR::HALFDUPLEX,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `FULLDUPLEX`"]
#[inline(always)]
pub fn is_full_duplex(&self) -> bool {
*self == COMMR::FULLDUPLEX
}
#[doc = "Checks if the value of the field is `TRANSMITTER`"]
#[inline(always)]
pub fn is_transmitter(&self) -> bool {
*self == COMMR::TRANSMITTER
}
#[doc = "Checks if the value of the field is `RECEIVER`"]
#[inline(always)]
pub fn is_receiver(&self) -> bool {
*self == COMMR::RECEIVER
}
#[doc = "Checks if the value of the field is `HALFDUPLEX`"]
#[inline(always)]
pub fn is_half_duplex(&self) -> bool {
*self == COMMR::HALFDUPLEX
}
}
#[doc = "Values that can be written to the field `COMM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COMMW {
#[doc = "Full duplex"]
FULLDUPLEX,
#[doc = "Simplex transmitter only"]
TRANSMITTER,
#[doc = "Simplex receiver only"]
RECEIVER,
#[doc = "Half duplex"]
HALFDUPLEX,
}
impl COMMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
COMMW::FULLDUPLEX => 0,
COMMW::TRANSMITTER => 1,
COMMW::RECEIVER => 2,
COMMW::HALFDUPLEX => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _COMMW<'a> {
w: &'a mut W,
}
impl<'a> _COMMW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: COMMW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Full duplex"]
#[inline(always)]
pub fn full_duplex(self) -> &'a mut W {
self.variant(COMMW::FULLDUPLEX)
}
#[doc = "Simplex transmitter only"]
#[inline(always)]
pub fn transmitter(self) -> &'a mut W {
self.variant(COMMW::TRANSMITTER)
}
#[doc = "Simplex receiver only"]
#[inline(always)]
pub fn receiver(self) -> &'a mut W {
self.variant(COMMW::RECEIVER)
}
#[doc = "Half duplex"]
#[inline(always)]
pub fn half_duplex(self) -> &'a mut W {
self.variant(COMMW::HALFDUPLEX)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 17);
self.w.bits |= ((value as u32) & 0x03) << 17;
self.w
}
}
#[doc = "Possible values of the field `IOSWP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IOSWPR {
#[doc = "MISO and MOSI not swapped"]
DISABLED,
#[doc = "MISO and MOSI swapped"]
ENABLED,
}
impl IOSWPR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
IOSWPR::DISABLED => false,
IOSWPR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> IOSWPR {
match value {
false => IOSWPR::DISABLED,
true => IOSWPR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == IOSWPR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == IOSWPR::ENABLED
}
}
#[doc = "Values that can be written to the field `IOSWP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IOSWPW {
#[doc = "MISO and MOSI not swapped"]
DISABLED,
#[doc = "MISO and MOSI swapped"]
ENABLED,
}
impl IOSWPW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
IOSWPW::DISABLED => false,
IOSWPW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _IOSWPW<'a> {
w: &'a mut W,
}
impl<'a> _IOSWPW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: IOSWPW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "MISO and MOSI not swapped"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(IOSWPW::DISABLED)
}
#[doc = "MISO and MOSI swapped"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(IOSWPW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 15);
self.w.bits |= ((value as u32) & 0x01) << 15;
self.w
}
}
#[doc = r"Value of the field"]
pub struct MIDIR {
bits: u8,
}
impl MIDIR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _MIDIW<'a> {
w: &'a mut W,
}
impl<'a> _MIDIW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 4);
self.w.bits |= ((value as u32) & 0x0f) << 4;
self.w
}
}
#[doc = r"Value of the field"]
pub struct MSSIR {
bits: u8,
}
impl MSSIR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _MSSIW<'a> {
w: &'a mut W,
}
impl<'a> _MSSIW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x0f << 0);
self.w.bits |= ((value as u32) & 0x0f) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 31 - Alternate function GPIOs control"]
#[inline(always)]
pub fn afcntr(&self) -> AFCNTRR {
AFCNTRR::_from(((self.bits >> 31) & 0x01) != 0)
}
#[doc = "Bit 30 - SS output management in master mode"]
#[inline(always)]
pub fn ssom(&self) -> SSOMR {
SSOMR::_from(((self.bits >> 30) & 0x01) != 0)
}
#[doc = "Bit 29 - SS output enable"]
#[inline(always)]
pub fn ssoe(&self) -> SSOER {
SSOER::_from(((self.bits >> 29) & 0x01) != 0)
}
#[doc = "Bit 28 - SS input/output polarity"]
#[inline(always)]
pub fn ssiop(&self) -> SSIOPR {
SSIOPR::_from(((self.bits >> 28) & 0x01) != 0)
}
#[doc = "Bit 26 - Software management of SS signal input"]
#[inline(always)]
pub fn ssm(&self) -> SSMR {
SSMR::_from(((self.bits >> 26) & 0x01) != 0)
}
#[doc = "Bit 25 - Clock polarity"]
#[inline(always)]
pub fn cpol(&self) -> CPOLR {
CPOLR::_from(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 24 - Clock phase"]
#[inline(always)]
pub fn cpha(&self) -> CPHAR {
CPHAR::_from(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 23 - Data frame format"]
#[inline(always)]
pub fn lsbfrst(&self) -> LSBFRSTR {
LSBFRSTR::_from(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 22 - SPI Master"]
#[inline(always)]
pub fn master(&self) -> MASTERR {
MASTERR::_from(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bits 19:21 - Serial Protocol"]
#[inline(always)]
pub fn sp(&self) -> SPR {
SPR::_from(((self.bits >> 19) & 0x07) as u8)
}
#[doc = "Bits 17:18 - SPI Communication Mode"]
#[inline(always)]
pub fn comm(&self) -> COMMR {
COMMR::_from(((self.bits >> 17) & 0x03) as u8)
}
#[doc = "Bit 15 - Swap functionality of MISO and MOSI pins"]
#[inline(always)]
pub fn ioswp(&self) -> IOSWPR {
IOSWPR::_from(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bits 4:7 - Master Inter-Data Idleness"]
#[inline(always)]
pub fn midi(&self) -> MIDIR {
let bits = ((self.bits >> 4) & 0x0f) as u8;
MIDIR { bits }
}
#[doc = "Bits 0:3 - Master SS Idleness"]
#[inline(always)]
pub fn mssi(&self) -> MSSIR {
let bits = ((self.bits >> 0) & 0x0f) as u8;
MSSIR { bits }
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 31 - Alternate function GPIOs control"]
#[inline(always)]
pub fn afcntr(&mut self) -> _AFCNTRW {
_AFCNTRW { w: self }
}
#[doc = "Bit 30 - SS output management in master mode"]
#[inline(always)]
pub fn ssom(&mut self) -> _SSOMW {
_SSOMW { w: self }
}
#[doc = "Bit 29 - SS output enable"]
#[inline(always)]
pub fn ssoe(&mut self) -> _SSOEW {
_SSOEW { w: self }
}
#[doc = "Bit 28 - SS input/output polarity"]
#[inline(always)]
pub fn ssiop(&mut self) -> _SSIOPW {
_SSIOPW { w: self }
}
#[doc = "Bit 26 - Software management of SS signal input"]
#[inline(always)]
pub fn ssm(&mut self) -> _SSMW {
_SSMW { w: self }
}
#[doc = "Bit 25 - Clock polarity"]
#[inline(always)]
pub fn cpol(&mut self) -> _CPOLW {
_CPOLW { w: self }
}
#[doc = "Bit 24 - Clock phase"]
#[inline(always)]
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
#[doc = "Bit 23 - Data frame format"]
#[inline(always)]
pub fn lsbfrst(&mut self) -> _LSBFRSTW {
_LSBFRSTW { w: self }
}
#[doc = "Bit 22 - SPI Master"]
#[inline(always)]
pub fn master(&mut self) -> _MASTERW {
_MASTERW { w: self }
}
#[doc = "Bits 19:21 - Serial Protocol"]
#[inline(always)]
pub fn sp(&mut self) -> _SPW {
_SPW { w: self }
}
#[doc = "Bits 17:18 - SPI Communication Mode"]
#[inline(always)]
pub fn comm(&mut self) -> _COMMW {
_COMMW { w: self }
}
#[doc = "Bit 15 - Swap functionality of MISO and MOSI pins"]
#[inline(always)]
pub fn ioswp(&mut self) -> _IOSWPW {
_IOSWPW { w: self }
}
#[doc = "Bits 4:7 - Master Inter-Data Idleness"]
#[inline(always)]
pub fn midi(&mut self) -> _MIDIW {
_MIDIW { w: self }
}
#[doc = "Bits 0:3 - Master SS Idleness"]
#[inline(always)]
pub fn mssi(&mut self) -> _MSSIW {
_MSSIW { w: self }
}
}