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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::PLL2DIVR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0x0101_0280 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Value of the field"] pub struct DIVN1R { bits: u16, } impl DIVN1R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u16 { self.bits } } #[doc = r"Proxy"] pub struct _DIVN1W<'a> { w: &'a mut W, } impl<'a> _DIVN1W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits &= !(0x01ff << 0); self.w.bits |= ((value as u32) & 0x01ff) << 0; self.w } } #[doc = r"Value of the field"] pub struct DIVP1R { bits: u8, } impl DIVP1R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVP1W<'a> { w: &'a mut W, } impl<'a> _DIVP1W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x7f << 9); self.w.bits |= ((value as u32) & 0x7f) << 9; self.w } } #[doc = r"Value of the field"] pub struct DIVQ1R { bits: u8, } impl DIVQ1R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVQ1W<'a> { w: &'a mut W, } impl<'a> _DIVQ1W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x7f << 16); self.w.bits |= ((value as u32) & 0x7f) << 16; self.w } } #[doc = r"Value of the field"] pub struct DIVR1R { bits: u8, } impl DIVR1R { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _DIVR1W<'a> { w: &'a mut W, } impl<'a> _DIVR1W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x7f << 24); self.w.bits |= ((value as u32) & 0x7f) << 24; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:8 - Multiplication factor for PLL1 VCO"] #[inline(always)] pub fn divn1(&self) -> DIVN1R { let bits = ((self.bits >> 0) & 0x01ff) as u16; DIVN1R { bits } } #[doc = "Bits 9:15 - PLL1 DIVP division factor"] #[inline(always)] pub fn divp1(&self) -> DIVP1R { let bits = ((self.bits >> 9) & 0x7f) as u8; DIVP1R { bits } } #[doc = "Bits 16:22 - PLL1 DIVQ division factor"] #[inline(always)] pub fn divq1(&self) -> DIVQ1R { let bits = ((self.bits >> 16) & 0x7f) as u8; DIVQ1R { bits } } #[doc = "Bits 24:30 - PLL1 DIVR division factor"] #[inline(always)] pub fn divr1(&self) -> DIVR1R { let bits = ((self.bits >> 24) & 0x7f) as u8; DIVR1R { bits } } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:8 - Multiplication factor for PLL1 VCO"] #[inline(always)] pub fn divn1(&mut self) -> _DIVN1W { _DIVN1W { w: self } } #[doc = "Bits 9:15 - PLL1 DIVP division factor"] #[inline(always)] pub fn divp1(&mut self) -> _DIVP1W { _DIVP1W { w: self } } #[doc = "Bits 16:22 - PLL1 DIVQ division factor"] #[inline(always)] pub fn divq1(&mut self) -> _DIVQ1W { _DIVQ1W { w: self } } #[doc = "Bits 24:30 - PLL1 DIVR division factor"] #[inline(always)] pub fn divr1(&mut self) -> _DIVR1W { _DIVR1W { w: self } } }