#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::D3CCIPR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `LPUART1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPUART1SELR {
#[doc = "rcc_pclk_d3 selected as peripheral clock"]
RCC_PCLK_D3,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl LPUART1SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
LPUART1SELR::RCC_PCLK_D3 => 0,
LPUART1SELR::PLL2_Q => 0x01,
LPUART1SELR::PLL3_Q => 0x02,
LPUART1SELR::HSI_KER => 0x03,
LPUART1SELR::CSI_KER => 0x04,
LPUART1SELR::LSE => 0x05,
LPUART1SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> LPUART1SELR {
match value {
0 => LPUART1SELR::RCC_PCLK_D3,
1 => LPUART1SELR::PLL2_Q,
2 => LPUART1SELR::PLL3_Q,
3 => LPUART1SELR::HSI_KER,
4 => LPUART1SELR::CSI_KER,
5 => LPUART1SELR::LSE,
i => LPUART1SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK_D3`"]
#[inline(always)]
pub fn is_rcc_pclk_d3(&self) -> bool {
*self == LPUART1SELR::RCC_PCLK_D3
}
#[doc = "Checks if the value of the field is `PLL2_Q`"]
#[inline(always)]
pub fn is_pll2_q(&self) -> bool {
*self == LPUART1SELR::PLL2_Q
}
#[doc = "Checks if the value of the field is `PLL3_Q`"]
#[inline(always)]
pub fn is_pll3_q(&self) -> bool {
*self == LPUART1SELR::PLL3_Q
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == LPUART1SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == LPUART1SELR::CSI_KER
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == LPUART1SELR::LSE
}
}
#[doc = "Values that can be written to the field `LPUART1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPUART1SELW {
#[doc = "rcc_pclk_d3 selected as peripheral clock"]
RCC_PCLK_D3,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "LSE selected as peripheral clock"]
LSE,
}
impl LPUART1SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
LPUART1SELW::RCC_PCLK_D3 => 0,
LPUART1SELW::PLL2_Q => 1,
LPUART1SELW::PLL3_Q => 2,
LPUART1SELW::HSI_KER => 3,
LPUART1SELW::CSI_KER => 4,
LPUART1SELW::LSE => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _LPUART1SELW<'a> {
w: &'a mut W,
}
impl<'a> _LPUART1SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: LPUART1SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk_d3 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk_d3(self) -> &'a mut W {
self.variant(LPUART1SELW::RCC_PCLK_D3)
}
#[doc = "pll2_q selected as peripheral clock"]
#[inline(always)]
pub fn pll2_q(self) -> &'a mut W {
self.variant(LPUART1SELW::PLL2_Q)
}
#[doc = "pll3_q selected as peripheral clock"]
#[inline(always)]
pub fn pll3_q(self) -> &'a mut W {
self.variant(LPUART1SELW::PLL3_Q)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(LPUART1SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(LPUART1SELW::CSI_KER)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(LPUART1SELW::LSE)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 0);
self.w.bits |= ((value as u32) & 0x07) << 0;
self.w
}
}
#[doc = "Possible values of the field `I2C4SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C4SELR {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
}
impl I2C4SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
I2C4SELR::RCC_PCLK4 => 0,
I2C4SELR::PLL3_R => 0x01,
I2C4SELR::HSI_KER => 0x02,
I2C4SELR::CSI_KER => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> I2C4SELR {
match value {
0 => I2C4SELR::RCC_PCLK4,
1 => I2C4SELR::PLL3_R,
2 => I2C4SELR::HSI_KER,
3 => I2C4SELR::CSI_KER,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK4`"]
#[inline(always)]
pub fn is_rcc_pclk4(&self) -> bool {
*self == I2C4SELR::RCC_PCLK4
}
#[doc = "Checks if the value of the field is `PLL3_R`"]
#[inline(always)]
pub fn is_pll3_r(&self) -> bool {
*self == I2C4SELR::PLL3_R
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == I2C4SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == I2C4SELR::CSI_KER
}
}
#[doc = "Values that can be written to the field `I2C4SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C4SELW {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
}
impl I2C4SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
I2C4SELW::RCC_PCLK4 => 0,
I2C4SELW::PLL3_R => 1,
I2C4SELW::HSI_KER => 2,
I2C4SELW::CSI_KER => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _I2C4SELW<'a> {
w: &'a mut W,
}
impl<'a> _I2C4SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C4SELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "rcc_pclk4 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk4(self) -> &'a mut W {
self.variant(I2C4SELW::RCC_PCLK4)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(I2C4SELW::PLL3_R)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(I2C4SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(I2C4SELW::CSI_KER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 8);
self.w.bits |= ((value as u32) & 0x03) << 8;
self.w
}
}
#[doc = "Possible values of the field `LPTIM2SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTIM2SELR {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "PER selected as peripheral clock"]
PER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl LPTIM2SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
LPTIM2SELR::RCC_PCLK4 => 0,
LPTIM2SELR::PLL2_P => 0x01,
LPTIM2SELR::PLL3_R => 0x02,
LPTIM2SELR::LSE => 0x03,
LPTIM2SELR::LSI => 0x04,
LPTIM2SELR::PER => 0x05,
LPTIM2SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> LPTIM2SELR {
match value {
0 => LPTIM2SELR::RCC_PCLK4,
1 => LPTIM2SELR::PLL2_P,
2 => LPTIM2SELR::PLL3_R,
3 => LPTIM2SELR::LSE,
4 => LPTIM2SELR::LSI,
5 => LPTIM2SELR::PER,
i => LPTIM2SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK4`"]
#[inline(always)]
pub fn is_rcc_pclk4(&self) -> bool {
*self == LPTIM2SELR::RCC_PCLK4
}
#[doc = "Checks if the value of the field is `PLL2_P`"]
#[inline(always)]
pub fn is_pll2_p(&self) -> bool {
*self == LPTIM2SELR::PLL2_P
}
#[doc = "Checks if the value of the field is `PLL3_R`"]
#[inline(always)]
pub fn is_pll3_r(&self) -> bool {
*self == LPTIM2SELR::PLL3_R
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == LPTIM2SELR::LSE
}
#[doc = "Checks if the value of the field is `LSI`"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == LPTIM2SELR::LSI
}
#[doc = "Checks if the value of the field is `PER`"]
#[inline(always)]
pub fn is_per(&self) -> bool {
*self == LPTIM2SELR::PER
}
}
#[doc = "Values that can be written to the field `LPTIM2SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTIM2SELW {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "LSE selected as peripheral clock"]
LSE,
#[doc = "LSI selected as peripheral clock"]
LSI,
#[doc = "PER selected as peripheral clock"]
PER,
}
impl LPTIM2SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
LPTIM2SELW::RCC_PCLK4 => 0,
LPTIM2SELW::PLL2_P => 1,
LPTIM2SELW::PLL3_R => 2,
LPTIM2SELW::LSE => 3,
LPTIM2SELW::LSI => 4,
LPTIM2SELW::PER => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _LPTIM2SELW<'a> {
w: &'a mut W,
}
impl<'a> _LPTIM2SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: LPTIM2SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk4 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk4(self) -> &'a mut W {
self.variant(LPTIM2SELW::RCC_PCLK4)
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(LPTIM2SELW::PLL2_P)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(LPTIM2SELW::PLL3_R)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(LPTIM2SELW::LSE)
}
#[doc = "LSI selected as peripheral clock"]
#[inline(always)]
pub fn lsi(self) -> &'a mut W {
self.variant(LPTIM2SELW::LSI)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(LPTIM2SELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 10);
self.w.bits |= ((value as u32) & 0x07) << 10;
self.w
}
}
#[doc = "Possible values of the field `LPTIM345SEL`"]
pub type LPTIM345SELR = LPTIM2SELR;
#[doc = "Values that can be written to the field `LPTIM345SEL`"]
pub type LPTIM345SELW = LPTIM2SELW;
#[doc = r"Proxy"]
pub struct _LPTIM345SELW<'a> {
w: &'a mut W,
}
impl<'a> _LPTIM345SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: LPTIM345SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk4 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk4(self) -> &'a mut W {
self.variant(LPTIM2SELW::RCC_PCLK4)
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(LPTIM2SELW::PLL2_P)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(LPTIM2SELW::PLL3_R)
}
#[doc = "LSE selected as peripheral clock"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(LPTIM2SELW::LSE)
}
#[doc = "LSI selected as peripheral clock"]
#[inline(always)]
pub fn lsi(self) -> &'a mut W {
self.variant(LPTIM2SELW::LSI)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(LPTIM2SELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 13);
self.w.bits |= ((value as u32) & 0x07) << 13;
self.w
}
}
#[doc = "Possible values of the field `ADCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCSELR {
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "PER selected as peripheral clock"]
PER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl ADCSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
ADCSELR::PLL2_P => 0,
ADCSELR::PLL3_R => 0x01,
ADCSELR::PER => 0x02,
ADCSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> ADCSELR {
match value {
0 => ADCSELR::PLL2_P,
1 => ADCSELR::PLL3_R,
2 => ADCSELR::PER,
i => ADCSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `PLL2_P`"]
#[inline(always)]
pub fn is_pll2_p(&self) -> bool {
*self == ADCSELR::PLL2_P
}
#[doc = "Checks if the value of the field is `PLL3_R`"]
#[inline(always)]
pub fn is_pll3_r(&self) -> bool {
*self == ADCSELR::PLL3_R
}
#[doc = "Checks if the value of the field is `PER`"]
#[inline(always)]
pub fn is_per(&self) -> bool {
*self == ADCSELR::PER
}
}
#[doc = "Values that can be written to the field `ADCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCSELW {
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_r selected as peripheral clock"]
PLL3_R,
#[doc = "PER selected as peripheral clock"]
PER,
}
impl ADCSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
ADCSELW::PLL2_P => 0,
ADCSELW::PLL3_R => 1,
ADCSELW::PER => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _ADCSELW<'a> {
w: &'a mut W,
}
impl<'a> _ADCSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADCSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(ADCSELW::PLL2_P)
}
#[doc = "pll3_r selected as peripheral clock"]
#[inline(always)]
pub fn pll3_r(self) -> &'a mut W {
self.variant(ADCSELW::PLL3_R)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(ADCSELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 16);
self.w.bits |= ((value as u32) & 0x03) << 16;
self.w
}
}
#[doc = "Possible values of the field `SAI4ASEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI4ASELR {
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_p selected as peripheral clock"]
PLL3_P,
#[doc = "i2s_ckin selected as peripheral clock"]
I2S_CKIN,
#[doc = "PER selected as peripheral clock"]
PER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SAI4ASELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SAI4ASELR::PLL1_Q => 0,
SAI4ASELR::PLL2_P => 0x01,
SAI4ASELR::PLL3_P => 0x02,
SAI4ASELR::I2S_CKIN => 0x03,
SAI4ASELR::PER => 0x04,
SAI4ASELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SAI4ASELR {
match value {
0 => SAI4ASELR::PLL1_Q,
1 => SAI4ASELR::PLL2_P,
2 => SAI4ASELR::PLL3_P,
3 => SAI4ASELR::I2S_CKIN,
4 => SAI4ASELR::PER,
i => SAI4ASELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `PLL1_Q`"]
#[inline(always)]
pub fn is_pll1_q(&self) -> bool {
*self == SAI4ASELR::PLL1_Q
}
#[doc = "Checks if the value of the field is `PLL2_P`"]
#[inline(always)]
pub fn is_pll2_p(&self) -> bool {
*self == SAI4ASELR::PLL2_P
}
#[doc = "Checks if the value of the field is `PLL3_P`"]
#[inline(always)]
pub fn is_pll3_p(&self) -> bool {
*self == SAI4ASELR::PLL3_P
}
#[doc = "Checks if the value of the field is `I2S_CKIN`"]
#[inline(always)]
pub fn is_i2s_ckin(&self) -> bool {
*self == SAI4ASELR::I2S_CKIN
}
#[doc = "Checks if the value of the field is `PER`"]
#[inline(always)]
pub fn is_per(&self) -> bool {
*self == SAI4ASELR::PER
}
}
#[doc = "Values that can be written to the field `SAI4ASEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI4ASELW {
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_p selected as peripheral clock"]
PLL3_P,
#[doc = "i2s_ckin selected as peripheral clock"]
I2S_CKIN,
#[doc = "PER selected as peripheral clock"]
PER,
}
impl SAI4ASELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SAI4ASELW::PLL1_Q => 0,
SAI4ASELW::PLL2_P => 1,
SAI4ASELW::PLL3_P => 2,
SAI4ASELW::I2S_CKIN => 3,
SAI4ASELW::PER => 4,
}
}
}
#[doc = r"Proxy"]
pub struct _SAI4ASELW<'a> {
w: &'a mut W,
}
impl<'a> _SAI4ASELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SAI4ASELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "pll1_q selected as peripheral clock"]
#[inline(always)]
pub fn pll1_q(self) -> &'a mut W {
self.variant(SAI4ASELW::PLL1_Q)
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(SAI4ASELW::PLL2_P)
}
#[doc = "pll3_p selected as peripheral clock"]
#[inline(always)]
pub fn pll3_p(self) -> &'a mut W {
self.variant(SAI4ASELW::PLL3_P)
}
#[doc = "i2s_ckin selected as peripheral clock"]
#[inline(always)]
pub fn i2s_ckin(self) -> &'a mut W {
self.variant(SAI4ASELW::I2S_CKIN)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(SAI4ASELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 21);
self.w.bits |= ((value as u32) & 0x07) << 21;
self.w
}
}
#[doc = "Possible values of the field `SAI4BSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI4BSELR {
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_p selected as peripheral clock"]
PLL3_P,
#[doc = "i2s_ckin selected as peripheral clock"]
I2S_CKIN,
#[doc = "PER selected as peripheral clock"]
PER,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SAI4BSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SAI4BSELR::PLL1_Q => 0,
SAI4BSELR::PLL2_P => 0x01,
SAI4BSELR::PLL3_P => 0x02,
SAI4BSELR::I2S_CKIN => 0x03,
SAI4BSELR::PER => 0x04,
SAI4BSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SAI4BSELR {
match value {
0 => SAI4BSELR::PLL1_Q,
1 => SAI4BSELR::PLL2_P,
2 => SAI4BSELR::PLL3_P,
3 => SAI4BSELR::I2S_CKIN,
4 => SAI4BSELR::PER,
i => SAI4BSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `PLL1_Q`"]
#[inline(always)]
pub fn is_pll1_q(&self) -> bool {
*self == SAI4BSELR::PLL1_Q
}
#[doc = "Checks if the value of the field is `PLL2_P`"]
#[inline(always)]
pub fn is_pll2_p(&self) -> bool {
*self == SAI4BSELR::PLL2_P
}
#[doc = "Checks if the value of the field is `PLL3_P`"]
#[inline(always)]
pub fn is_pll3_p(&self) -> bool {
*self == SAI4BSELR::PLL3_P
}
#[doc = "Checks if the value of the field is `I2S_CKIN`"]
#[inline(always)]
pub fn is_i2s_ckin(&self) -> bool {
*self == SAI4BSELR::I2S_CKIN
}
#[doc = "Checks if the value of the field is `PER`"]
#[inline(always)]
pub fn is_per(&self) -> bool {
*self == SAI4BSELR::PER
}
}
#[doc = "Values that can be written to the field `SAI4BSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SAI4BSELW {
#[doc = "pll1_q selected as peripheral clock"]
PLL1_Q,
#[doc = "pll2_p selected as peripheral clock"]
PLL2_P,
#[doc = "pll3_p selected as peripheral clock"]
PLL3_P,
#[doc = "i2s_ckin selected as peripheral clock"]
I2S_CKIN,
#[doc = "PER selected as peripheral clock"]
PER,
}
impl SAI4BSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SAI4BSELW::PLL1_Q => 0,
SAI4BSELW::PLL2_P => 1,
SAI4BSELW::PLL3_P => 2,
SAI4BSELW::I2S_CKIN => 3,
SAI4BSELW::PER => 4,
}
}
}
#[doc = r"Proxy"]
pub struct _SAI4BSELW<'a> {
w: &'a mut W,
}
impl<'a> _SAI4BSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SAI4BSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "pll1_q selected as peripheral clock"]
#[inline(always)]
pub fn pll1_q(self) -> &'a mut W {
self.variant(SAI4BSELW::PLL1_Q)
}
#[doc = "pll2_p selected as peripheral clock"]
#[inline(always)]
pub fn pll2_p(self) -> &'a mut W {
self.variant(SAI4BSELW::PLL2_P)
}
#[doc = "pll3_p selected as peripheral clock"]
#[inline(always)]
pub fn pll3_p(self) -> &'a mut W {
self.variant(SAI4BSELW::PLL3_P)
}
#[doc = "i2s_ckin selected as peripheral clock"]
#[inline(always)]
pub fn i2s_ckin(self) -> &'a mut W {
self.variant(SAI4BSELW::I2S_CKIN)
}
#[doc = "PER selected as peripheral clock"]
#[inline(always)]
pub fn per(self) -> &'a mut W {
self.variant(SAI4BSELW::PER)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 24);
self.w.bits |= ((value as u32) & 0x07) << 24;
self.w
}
}
#[doc = "Possible values of the field `SPI6SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI6SELR {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "HSE selected as peripheral clock"]
HSE,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SPI6SELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SPI6SELR::RCC_PCLK4 => 0,
SPI6SELR::PLL2_Q => 0x01,
SPI6SELR::PLL3_Q => 0x02,
SPI6SELR::HSI_KER => 0x03,
SPI6SELR::CSI_KER => 0x04,
SPI6SELR::HSE => 0x05,
SPI6SELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SPI6SELR {
match value {
0 => SPI6SELR::RCC_PCLK4,
1 => SPI6SELR::PLL2_Q,
2 => SPI6SELR::PLL3_Q,
3 => SPI6SELR::HSI_KER,
4 => SPI6SELR::CSI_KER,
5 => SPI6SELR::HSE,
i => SPI6SELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RCC_PCLK4`"]
#[inline(always)]
pub fn is_rcc_pclk4(&self) -> bool {
*self == SPI6SELR::RCC_PCLK4
}
#[doc = "Checks if the value of the field is `PLL2_Q`"]
#[inline(always)]
pub fn is_pll2_q(&self) -> bool {
*self == SPI6SELR::PLL2_Q
}
#[doc = "Checks if the value of the field is `PLL3_Q`"]
#[inline(always)]
pub fn is_pll3_q(&self) -> bool {
*self == SPI6SELR::PLL3_Q
}
#[doc = "Checks if the value of the field is `HSI_KER`"]
#[inline(always)]
pub fn is_hsi_ker(&self) -> bool {
*self == SPI6SELR::HSI_KER
}
#[doc = "Checks if the value of the field is `CSI_KER`"]
#[inline(always)]
pub fn is_csi_ker(&self) -> bool {
*self == SPI6SELR::CSI_KER
}
#[doc = "Checks if the value of the field is `HSE`"]
#[inline(always)]
pub fn is_hse(&self) -> bool {
*self == SPI6SELR::HSE
}
}
#[doc = "Values that can be written to the field `SPI6SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI6SELW {
#[doc = "rcc_pclk4 selected as peripheral clock"]
RCC_PCLK4,
#[doc = "pll2_q selected as peripheral clock"]
PLL2_Q,
#[doc = "pll3_q selected as peripheral clock"]
PLL3_Q,
#[doc = "hsi_ker selected as peripheral clock"]
HSI_KER,
#[doc = "csi_ker selected as peripheral clock"]
CSI_KER,
#[doc = "HSE selected as peripheral clock"]
HSE,
}
impl SPI6SELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SPI6SELW::RCC_PCLK4 => 0,
SPI6SELW::PLL2_Q => 1,
SPI6SELW::PLL3_Q => 2,
SPI6SELW::HSI_KER => 3,
SPI6SELW::CSI_KER => 4,
SPI6SELW::HSE => 5,
}
}
}
#[doc = r"Proxy"]
pub struct _SPI6SELW<'a> {
w: &'a mut W,
}
impl<'a> _SPI6SELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPI6SELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "rcc_pclk4 selected as peripheral clock"]
#[inline(always)]
pub fn rcc_pclk4(self) -> &'a mut W {
self.variant(SPI6SELW::RCC_PCLK4)
}
#[doc = "pll2_q selected as peripheral clock"]
#[inline(always)]
pub fn pll2_q(self) -> &'a mut W {
self.variant(SPI6SELW::PLL2_Q)
}
#[doc = "pll3_q selected as peripheral clock"]
#[inline(always)]
pub fn pll3_q(self) -> &'a mut W {
self.variant(SPI6SELW::PLL3_Q)
}
#[doc = "hsi_ker selected as peripheral clock"]
#[inline(always)]
pub fn hsi_ker(self) -> &'a mut W {
self.variant(SPI6SELW::HSI_KER)
}
#[doc = "csi_ker selected as peripheral clock"]
#[inline(always)]
pub fn csi_ker(self) -> &'a mut W {
self.variant(SPI6SELW::CSI_KER)
}
#[doc = "HSE selected as peripheral clock"]
#[inline(always)]
pub fn hse(self) -> &'a mut W {
self.variant(SPI6SELW::HSE)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 28);
self.w.bits |= ((value as u32) & 0x07) << 28;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - LPUART1 kernel clock source selection"]
#[inline(always)]
pub fn lpuart1sel(&self) -> LPUART1SELR {
LPUART1SELR::_from(((self.bits >> 0) & 0x07) as u8)
}
#[doc = "Bits 8:9 - I2C4 kernel clock source selection"]
#[inline(always)]
pub fn i2c4sel(&self) -> I2C4SELR {
I2C4SELR::_from(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bits 10:12 - LPTIM2 kernel clock source selection"]
#[inline(always)]
pub fn lptim2sel(&self) -> LPTIM2SELR {
LPTIM2SELR::_from(((self.bits >> 10) & 0x07) as u8)
}
#[doc = "Bits 13:15 - LPTIM3,4,5 kernel clock source selection"]
#[inline(always)]
pub fn lptim345sel(&self) -> LPTIM345SELR {
LPTIM345SELR::_from(((self.bits >> 13) & 0x07) as u8)
}
#[doc = "Bits 16:17 - SAR ADC kernel clock source selection"]
#[inline(always)]
pub fn adcsel(&self) -> ADCSELR {
ADCSELR::_from(((self.bits >> 16) & 0x03) as u8)
}
#[doc = "Bits 21:23 - Sub-Block A of SAI4 kernel clock source selection"]
#[inline(always)]
pub fn sai4asel(&self) -> SAI4ASELR {
SAI4ASELR::_from(((self.bits >> 21) & 0x07) as u8)
}
#[doc = "Bits 24:26 - Sub-Block B of SAI4 kernel clock source selection"]
#[inline(always)]
pub fn sai4bsel(&self) -> SAI4BSELR {
SAI4BSELR::_from(((self.bits >> 24) & 0x07) as u8)
}
#[doc = "Bits 28:30 - SPI6 kernel clock source selection"]
#[inline(always)]
pub fn spi6sel(&self) -> SPI6SELR {
SPI6SELR::_from(((self.bits >> 28) & 0x07) as u8)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - LPUART1 kernel clock source selection"]
#[inline(always)]
pub fn lpuart1sel(&mut self) -> _LPUART1SELW {
_LPUART1SELW { w: self }
}
#[doc = "Bits 8:9 - I2C4 kernel clock source selection"]
#[inline(always)]
pub fn i2c4sel(&mut self) -> _I2C4SELW {
_I2C4SELW { w: self }
}
#[doc = "Bits 10:12 - LPTIM2 kernel clock source selection"]
#[inline(always)]
pub fn lptim2sel(&mut self) -> _LPTIM2SELW {
_LPTIM2SELW { w: self }
}
#[doc = "Bits 13:15 - LPTIM3,4,5 kernel clock source selection"]
#[inline(always)]
pub fn lptim345sel(&mut self) -> _LPTIM345SELW {
_LPTIM345SELW { w: self }
}
#[doc = "Bits 16:17 - SAR ADC kernel clock source selection"]
#[inline(always)]
pub fn adcsel(&mut self) -> _ADCSELW {
_ADCSELW { w: self }
}
#[doc = "Bits 21:23 - Sub-Block A of SAI4 kernel clock source selection"]
#[inline(always)]
pub fn sai4asel(&mut self) -> _SAI4ASELW {
_SAI4ASELW { w: self }
}
#[doc = "Bits 24:26 - Sub-Block B of SAI4 kernel clock source selection"]
#[inline(always)]
pub fn sai4bsel(&mut self) -> _SAI4BSELW {
_SAI4BSELW { w: self }
}
#[doc = "Bits 28:30 - SPI6 kernel clock source selection"]
#[inline(always)]
pub fn spi6sel(&mut self) -> _SPI6SELW {
_SPI6SELW { w: self }
}
}