#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::RGCR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `SIG_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIG_IDR {
#[doc = "Signal `dmamux2_evt0` selected as trigger input"]
DMAMUX2_EVT0,
#[doc = "Signal `dmamux2_evt1` selected as trigger input"]
DMAMUX2_EVT1,
#[doc = "Signal `dmamux2_evt2` selected as trigger input"]
DMAMUX2_EVT2,
#[doc = "Signal `dmamux2_evt3` selected as trigger input"]
DMAMUX2_EVT3,
#[doc = "Signal `dmamux2_evt4` selected as trigger input"]
DMAMUX2_EVT4,
#[doc = "Signal `dmamux2_evt5` selected as trigger input"]
DMAMUX2_EVT5,
#[doc = "Signal `dmamux2_evt6` selected as trigger input"]
DMAMUX2_EVT6,
#[doc = "Signal `lpuart_rx_wkup` selected as trigger input"]
LPUART_RX_WKUP,
#[doc = "Signal `lpuart_tx_wkup` selected as trigger input"]
LPUART_TX_WKUP,
#[doc = "Signal `lptim2_wkup` selected as trigger input"]
LPTIM2_WKUP,
#[doc = "Signal `lptim2_out` selected as trigger input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_wkup` selected as trigger input"]
LPTIM3_WKUP,
#[doc = "Signal `lptim3_out` selected as trigger input"]
LPTIM3_OUT,
#[doc = "Signal `lptim4_ait` selected as trigger input"]
LPTIM4_AIT,
#[doc = "Signal `lptim5_ait` selected as trigger input"]
LPTIM5_AIT,
#[doc = "Signal `i2c4_wkup` selected as trigger input"]
I2C4_WKUP,
#[doc = "Signal `spi6_wkup` selected as trigger input"]
SPI6_WKUP,
#[doc = "Signal `comp1_out` selected as trigger input"]
COMP1_OUT,
#[doc = "Signal `comp2_out` selected as trigger input"]
COMP2_OUT,
#[doc = "Signal `rtc_wkup` selected as trigger input"]
RTC_WKUP,
#[doc = "Signal `syscfg_exti0_mux` selected as trigger input"]
SYSCFG_EXTI0_MUX,
#[doc = "Signal `syscfg_exti2_mux` selected as trigger input"]
SYSCFG_EXTI2_MUX,
#[doc = "Signal `i2c4_event_it` selected as trigger input"]
I2C4_EVENT_IT,
#[doc = "Signal `spi6_it` selected as trigger input"]
SPI6_IT,
#[doc = "Signal `lpuart1_it_t` selected as trigger input"]
LPUART1_IT_T,
#[doc = "Signal `lpuart1_it_r` selected as trigger input"]
LPUART1_IT_R,
#[doc = "Signal `adc3_it` selected as trigger input"]
ADC3_IT,
#[doc = "Signal `adc3_awd1` selected as trigger input"]
ADC3_AWD1,
#[doc = "Signal `bdma_ch0_it` selected as trigger input"]
BDMA_CH0_IT,
#[doc = "Signal `bdma_ch1_it` selected as trigger input"]
BDMA_CH1_IT,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl SIG_IDR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
SIG_IDR::DMAMUX2_EVT0 => 0,
SIG_IDR::DMAMUX2_EVT1 => 0x01,
SIG_IDR::DMAMUX2_EVT2 => 0x02,
SIG_IDR::DMAMUX2_EVT3 => 0x03,
SIG_IDR::DMAMUX2_EVT4 => 0x04,
SIG_IDR::DMAMUX2_EVT5 => 0x05,
SIG_IDR::DMAMUX2_EVT6 => 0x06,
SIG_IDR::LPUART_RX_WKUP => 0x07,
SIG_IDR::LPUART_TX_WKUP => 0x08,
SIG_IDR::LPTIM2_WKUP => 0x09,
SIG_IDR::LPTIM2_OUT => 0x0a,
SIG_IDR::LPTIM3_WKUP => 0x0b,
SIG_IDR::LPTIM3_OUT => 0x0c,
SIG_IDR::LPTIM4_AIT => 0x0d,
SIG_IDR::LPTIM5_AIT => 0x0e,
SIG_IDR::I2C4_WKUP => 0x0f,
SIG_IDR::SPI6_WKUP => 0x10,
SIG_IDR::COMP1_OUT => 0x11,
SIG_IDR::COMP2_OUT => 0x12,
SIG_IDR::RTC_WKUP => 0x13,
SIG_IDR::SYSCFG_EXTI0_MUX => 0x14,
SIG_IDR::SYSCFG_EXTI2_MUX => 0x15,
SIG_IDR::I2C4_EVENT_IT => 0x16,
SIG_IDR::SPI6_IT => 0x17,
SIG_IDR::LPUART1_IT_T => 0x18,
SIG_IDR::LPUART1_IT_R => 0x19,
SIG_IDR::ADC3_IT => 0x1a,
SIG_IDR::ADC3_AWD1 => 0x1b,
SIG_IDR::BDMA_CH0_IT => 0x1c,
SIG_IDR::BDMA_CH1_IT => 0x1d,
SIG_IDR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> SIG_IDR {
match value {
0 => SIG_IDR::DMAMUX2_EVT0,
1 => SIG_IDR::DMAMUX2_EVT1,
2 => SIG_IDR::DMAMUX2_EVT2,
3 => SIG_IDR::DMAMUX2_EVT3,
4 => SIG_IDR::DMAMUX2_EVT4,
5 => SIG_IDR::DMAMUX2_EVT5,
6 => SIG_IDR::DMAMUX2_EVT6,
7 => SIG_IDR::LPUART_RX_WKUP,
8 => SIG_IDR::LPUART_TX_WKUP,
9 => SIG_IDR::LPTIM2_WKUP,
10 => SIG_IDR::LPTIM2_OUT,
11 => SIG_IDR::LPTIM3_WKUP,
12 => SIG_IDR::LPTIM3_OUT,
13 => SIG_IDR::LPTIM4_AIT,
14 => SIG_IDR::LPTIM5_AIT,
15 => SIG_IDR::I2C4_WKUP,
16 => SIG_IDR::SPI6_WKUP,
17 => SIG_IDR::COMP1_OUT,
18 => SIG_IDR::COMP2_OUT,
19 => SIG_IDR::RTC_WKUP,
20 => SIG_IDR::SYSCFG_EXTI0_MUX,
21 => SIG_IDR::SYSCFG_EXTI2_MUX,
22 => SIG_IDR::I2C4_EVENT_IT,
23 => SIG_IDR::SPI6_IT,
24 => SIG_IDR::LPUART1_IT_T,
25 => SIG_IDR::LPUART1_IT_R,
26 => SIG_IDR::ADC3_IT,
27 => SIG_IDR::ADC3_AWD1,
28 => SIG_IDR::BDMA_CH0_IT,
29 => SIG_IDR::BDMA_CH1_IT,
i => SIG_IDR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT0`"]
#[inline(always)]
pub fn is_dmamux2_evt0(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT0
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT1`"]
#[inline(always)]
pub fn is_dmamux2_evt1(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT1
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT2`"]
#[inline(always)]
pub fn is_dmamux2_evt2(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT2
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT3`"]
#[inline(always)]
pub fn is_dmamux2_evt3(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT3
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT4`"]
#[inline(always)]
pub fn is_dmamux2_evt4(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT4
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT5`"]
#[inline(always)]
pub fn is_dmamux2_evt5(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT5
}
#[doc = "Checks if the value of the field is `DMAMUX2_EVT6`"]
#[inline(always)]
pub fn is_dmamux2_evt6(&self) -> bool {
*self == SIG_IDR::DMAMUX2_EVT6
}
#[doc = "Checks if the value of the field is `LPUART_RX_WKUP`"]
#[inline(always)]
pub fn is_lpuart_rx_wkup(&self) -> bool {
*self == SIG_IDR::LPUART_RX_WKUP
}
#[doc = "Checks if the value of the field is `LPUART_TX_WKUP`"]
#[inline(always)]
pub fn is_lpuart_tx_wkup(&self) -> bool {
*self == SIG_IDR::LPUART_TX_WKUP
}
#[doc = "Checks if the value of the field is `LPTIM2_WKUP`"]
#[inline(always)]
pub fn is_lptim2_wkup(&self) -> bool {
*self == SIG_IDR::LPTIM2_WKUP
}
#[doc = "Checks if the value of the field is `LPTIM2_OUT`"]
#[inline(always)]
pub fn is_lptim2_out(&self) -> bool {
*self == SIG_IDR::LPTIM2_OUT
}
#[doc = "Checks if the value of the field is `LPTIM3_WKUP`"]
#[inline(always)]
pub fn is_lptim3_wkup(&self) -> bool {
*self == SIG_IDR::LPTIM3_WKUP
}
#[doc = "Checks if the value of the field is `LPTIM3_OUT`"]
#[inline(always)]
pub fn is_lptim3_out(&self) -> bool {
*self == SIG_IDR::LPTIM3_OUT
}
#[doc = "Checks if the value of the field is `LPTIM4_AIT`"]
#[inline(always)]
pub fn is_lptim4_ait(&self) -> bool {
*self == SIG_IDR::LPTIM4_AIT
}
#[doc = "Checks if the value of the field is `LPTIM5_AIT`"]
#[inline(always)]
pub fn is_lptim5_ait(&self) -> bool {
*self == SIG_IDR::LPTIM5_AIT
}
#[doc = "Checks if the value of the field is `I2C4_WKUP`"]
#[inline(always)]
pub fn is_i2c4_wkup(&self) -> bool {
*self == SIG_IDR::I2C4_WKUP
}
#[doc = "Checks if the value of the field is `SPI6_WKUP`"]
#[inline(always)]
pub fn is_spi6_wkup(&self) -> bool {
*self == SIG_IDR::SPI6_WKUP
}
#[doc = "Checks if the value of the field is `COMP1_OUT`"]
#[inline(always)]
pub fn is_comp1_out(&self) -> bool {
*self == SIG_IDR::COMP1_OUT
}
#[doc = "Checks if the value of the field is `COMP2_OUT`"]
#[inline(always)]
pub fn is_comp2_out(&self) -> bool {
*self == SIG_IDR::COMP2_OUT
}
#[doc = "Checks if the value of the field is `RTC_WKUP`"]
#[inline(always)]
pub fn is_rtc_wkup(&self) -> bool {
*self == SIG_IDR::RTC_WKUP
}
#[doc = "Checks if the value of the field is `SYSCFG_EXTI0_MUX`"]
#[inline(always)]
pub fn is_syscfg_exti0_mux(&self) -> bool {
*self == SIG_IDR::SYSCFG_EXTI0_MUX
}
#[doc = "Checks if the value of the field is `SYSCFG_EXTI2_MUX`"]
#[inline(always)]
pub fn is_syscfg_exti2_mux(&self) -> bool {
*self == SIG_IDR::SYSCFG_EXTI2_MUX
}
#[doc = "Checks if the value of the field is `I2C4_EVENT_IT`"]
#[inline(always)]
pub fn is_i2c4_event_it(&self) -> bool {
*self == SIG_IDR::I2C4_EVENT_IT
}
#[doc = "Checks if the value of the field is `SPI6_IT`"]
#[inline(always)]
pub fn is_spi6_it(&self) -> bool {
*self == SIG_IDR::SPI6_IT
}
#[doc = "Checks if the value of the field is `LPUART1_IT_T`"]
#[inline(always)]
pub fn is_lpuart1_it_t(&self) -> bool {
*self == SIG_IDR::LPUART1_IT_T
}
#[doc = "Checks if the value of the field is `LPUART1_IT_R`"]
#[inline(always)]
pub fn is_lpuart1_it_r(&self) -> bool {
*self == SIG_IDR::LPUART1_IT_R
}
#[doc = "Checks if the value of the field is `ADC3_IT`"]
#[inline(always)]
pub fn is_adc3_it(&self) -> bool {
*self == SIG_IDR::ADC3_IT
}
#[doc = "Checks if the value of the field is `ADC3_AWD1`"]
#[inline(always)]
pub fn is_adc3_awd1(&self) -> bool {
*self == SIG_IDR::ADC3_AWD1
}
#[doc = "Checks if the value of the field is `BDMA_CH0_IT`"]
#[inline(always)]
pub fn is_bdma_ch0_it(&self) -> bool {
*self == SIG_IDR::BDMA_CH0_IT
}
#[doc = "Checks if the value of the field is `BDMA_CH1_IT`"]
#[inline(always)]
pub fn is_bdma_ch1_it(&self) -> bool {
*self == SIG_IDR::BDMA_CH1_IT
}
}
#[doc = "Values that can be written to the field `SIG_ID`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIG_IDW {
#[doc = "Signal `dmamux2_evt0` selected as trigger input"]
DMAMUX2_EVT0,
#[doc = "Signal `dmamux2_evt1` selected as trigger input"]
DMAMUX2_EVT1,
#[doc = "Signal `dmamux2_evt2` selected as trigger input"]
DMAMUX2_EVT2,
#[doc = "Signal `dmamux2_evt3` selected as trigger input"]
DMAMUX2_EVT3,
#[doc = "Signal `dmamux2_evt4` selected as trigger input"]
DMAMUX2_EVT4,
#[doc = "Signal `dmamux2_evt5` selected as trigger input"]
DMAMUX2_EVT5,
#[doc = "Signal `dmamux2_evt6` selected as trigger input"]
DMAMUX2_EVT6,
#[doc = "Signal `lpuart_rx_wkup` selected as trigger input"]
LPUART_RX_WKUP,
#[doc = "Signal `lpuart_tx_wkup` selected as trigger input"]
LPUART_TX_WKUP,
#[doc = "Signal `lptim2_wkup` selected as trigger input"]
LPTIM2_WKUP,
#[doc = "Signal `lptim2_out` selected as trigger input"]
LPTIM2_OUT,
#[doc = "Signal `lptim3_wkup` selected as trigger input"]
LPTIM3_WKUP,
#[doc = "Signal `lptim3_out` selected as trigger input"]
LPTIM3_OUT,
#[doc = "Signal `lptim4_ait` selected as trigger input"]
LPTIM4_AIT,
#[doc = "Signal `lptim5_ait` selected as trigger input"]
LPTIM5_AIT,
#[doc = "Signal `i2c4_wkup` selected as trigger input"]
I2C4_WKUP,
#[doc = "Signal `spi6_wkup` selected as trigger input"]
SPI6_WKUP,
#[doc = "Signal `comp1_out` selected as trigger input"]
COMP1_OUT,
#[doc = "Signal `comp2_out` selected as trigger input"]
COMP2_OUT,
#[doc = "Signal `rtc_wkup` selected as trigger input"]
RTC_WKUP,
#[doc = "Signal `syscfg_exti0_mux` selected as trigger input"]
SYSCFG_EXTI0_MUX,
#[doc = "Signal `syscfg_exti2_mux` selected as trigger input"]
SYSCFG_EXTI2_MUX,
#[doc = "Signal `i2c4_event_it` selected as trigger input"]
I2C4_EVENT_IT,
#[doc = "Signal `spi6_it` selected as trigger input"]
SPI6_IT,
#[doc = "Signal `lpuart1_it_t` selected as trigger input"]
LPUART1_IT_T,
#[doc = "Signal `lpuart1_it_r` selected as trigger input"]
LPUART1_IT_R,
#[doc = "Signal `adc3_it` selected as trigger input"]
ADC3_IT,
#[doc = "Signal `adc3_awd1` selected as trigger input"]
ADC3_AWD1,
#[doc = "Signal `bdma_ch0_it` selected as trigger input"]
BDMA_CH0_IT,
#[doc = "Signal `bdma_ch1_it` selected as trigger input"]
BDMA_CH1_IT,
}
impl SIG_IDW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
SIG_IDW::DMAMUX2_EVT0 => 0,
SIG_IDW::DMAMUX2_EVT1 => 1,
SIG_IDW::DMAMUX2_EVT2 => 2,
SIG_IDW::DMAMUX2_EVT3 => 3,
SIG_IDW::DMAMUX2_EVT4 => 4,
SIG_IDW::DMAMUX2_EVT5 => 5,
SIG_IDW::DMAMUX2_EVT6 => 6,
SIG_IDW::LPUART_RX_WKUP => 7,
SIG_IDW::LPUART_TX_WKUP => 8,
SIG_IDW::LPTIM2_WKUP => 9,
SIG_IDW::LPTIM2_OUT => 10,
SIG_IDW::LPTIM3_WKUP => 11,
SIG_IDW::LPTIM3_OUT => 12,
SIG_IDW::LPTIM4_AIT => 13,
SIG_IDW::LPTIM5_AIT => 14,
SIG_IDW::I2C4_WKUP => 15,
SIG_IDW::SPI6_WKUP => 16,
SIG_IDW::COMP1_OUT => 17,
SIG_IDW::COMP2_OUT => 18,
SIG_IDW::RTC_WKUP => 19,
SIG_IDW::SYSCFG_EXTI0_MUX => 20,
SIG_IDW::SYSCFG_EXTI2_MUX => 21,
SIG_IDW::I2C4_EVENT_IT => 22,
SIG_IDW::SPI6_IT => 23,
SIG_IDW::LPUART1_IT_T => 24,
SIG_IDW::LPUART1_IT_R => 25,
SIG_IDW::ADC3_IT => 26,
SIG_IDW::ADC3_AWD1 => 27,
SIG_IDW::BDMA_CH0_IT => 28,
SIG_IDW::BDMA_CH1_IT => 29,
}
}
}
#[doc = r"Proxy"]
pub struct _SIG_IDW<'a> {
w: &'a mut W,
}
impl<'a> _SIG_IDW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SIG_IDW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Signal `dmamux2_evt0` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt0(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT0)
}
#[doc = "Signal `dmamux2_evt1` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt1(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT1)
}
#[doc = "Signal `dmamux2_evt2` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt2(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT2)
}
#[doc = "Signal `dmamux2_evt3` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt3(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT3)
}
#[doc = "Signal `dmamux2_evt4` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt4(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT4)
}
#[doc = "Signal `dmamux2_evt5` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt5(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT5)
}
#[doc = "Signal `dmamux2_evt6` selected as trigger input"]
#[inline(always)]
pub fn dmamux2_evt6(self) -> &'a mut W {
self.variant(SIG_IDW::DMAMUX2_EVT6)
}
#[doc = "Signal `lpuart_rx_wkup` selected as trigger input"]
#[inline(always)]
pub fn lpuart_rx_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::LPUART_RX_WKUP)
}
#[doc = "Signal `lpuart_tx_wkup` selected as trigger input"]
#[inline(always)]
pub fn lpuart_tx_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::LPUART_TX_WKUP)
}
#[doc = "Signal `lptim2_wkup` selected as trigger input"]
#[inline(always)]
pub fn lptim2_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM2_WKUP)
}
#[doc = "Signal `lptim2_out` selected as trigger input"]
#[inline(always)]
pub fn lptim2_out(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM2_OUT)
}
#[doc = "Signal `lptim3_wkup` selected as trigger input"]
#[inline(always)]
pub fn lptim3_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM3_WKUP)
}
#[doc = "Signal `lptim3_out` selected as trigger input"]
#[inline(always)]
pub fn lptim3_out(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM3_OUT)
}
#[doc = "Signal `lptim4_ait` selected as trigger input"]
#[inline(always)]
pub fn lptim4_ait(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM4_AIT)
}
#[doc = "Signal `lptim5_ait` selected as trigger input"]
#[inline(always)]
pub fn lptim5_ait(self) -> &'a mut W {
self.variant(SIG_IDW::LPTIM5_AIT)
}
#[doc = "Signal `i2c4_wkup` selected as trigger input"]
#[inline(always)]
pub fn i2c4_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::I2C4_WKUP)
}
#[doc = "Signal `spi6_wkup` selected as trigger input"]
#[inline(always)]
pub fn spi6_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::SPI6_WKUP)
}
#[doc = "Signal `comp1_out` selected as trigger input"]
#[inline(always)]
pub fn comp1_out(self) -> &'a mut W {
self.variant(SIG_IDW::COMP1_OUT)
}
#[doc = "Signal `comp2_out` selected as trigger input"]
#[inline(always)]
pub fn comp2_out(self) -> &'a mut W {
self.variant(SIG_IDW::COMP2_OUT)
}
#[doc = "Signal `rtc_wkup` selected as trigger input"]
#[inline(always)]
pub fn rtc_wkup(self) -> &'a mut W {
self.variant(SIG_IDW::RTC_WKUP)
}
#[doc = "Signal `syscfg_exti0_mux` selected as trigger input"]
#[inline(always)]
pub fn syscfg_exti0_mux(self) -> &'a mut W {
self.variant(SIG_IDW::SYSCFG_EXTI0_MUX)
}
#[doc = "Signal `syscfg_exti2_mux` selected as trigger input"]
#[inline(always)]
pub fn syscfg_exti2_mux(self) -> &'a mut W {
self.variant(SIG_IDW::SYSCFG_EXTI2_MUX)
}
#[doc = "Signal `i2c4_event_it` selected as trigger input"]
#[inline(always)]
pub fn i2c4_event_it(self) -> &'a mut W {
self.variant(SIG_IDW::I2C4_EVENT_IT)
}
#[doc = "Signal `spi6_it` selected as trigger input"]
#[inline(always)]
pub fn spi6_it(self) -> &'a mut W {
self.variant(SIG_IDW::SPI6_IT)
}
#[doc = "Signal `lpuart1_it_t` selected as trigger input"]
#[inline(always)]
pub fn lpuart1_it_t(self) -> &'a mut W {
self.variant(SIG_IDW::LPUART1_IT_T)
}
#[doc = "Signal `lpuart1_it_r` selected as trigger input"]
#[inline(always)]
pub fn lpuart1_it_r(self) -> &'a mut W {
self.variant(SIG_IDW::LPUART1_IT_R)
}
#[doc = "Signal `adc3_it` selected as trigger input"]
#[inline(always)]
pub fn adc3_it(self) -> &'a mut W {
self.variant(SIG_IDW::ADC3_IT)
}
#[doc = "Signal `adc3_awd1` selected as trigger input"]
#[inline(always)]
pub fn adc3_awd1(self) -> &'a mut W {
self.variant(SIG_IDW::ADC3_AWD1)
}
#[doc = "Signal `bdma_ch0_it` selected as trigger input"]
#[inline(always)]
pub fn bdma_ch0_it(self) -> &'a mut W {
self.variant(SIG_IDW::BDMA_CH0_IT)
}
#[doc = "Signal `bdma_ch1_it` selected as trigger input"]
#[inline(always)]
pub fn bdma_ch1_it(self) -> &'a mut W {
self.variant(SIG_IDW::BDMA_CH1_IT)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 0);
self.w.bits |= ((value as u32) & 0x1f) << 0;
self.w
}
}
#[doc = "Possible values of the field `OIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OIER {
#[doc = "Trigger overrun interrupt disabled"]
DISABLED,
#[doc = "Trigger overrun interrupt enabled"]
ENABLED,
}
impl OIER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
OIER::DISABLED => false,
OIER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> OIER {
match value {
false => OIER::DISABLED,
true => OIER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OIER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OIER::ENABLED
}
}
#[doc = "Values that can be written to the field `OIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OIEW {
#[doc = "Trigger overrun interrupt disabled"]
DISABLED,
#[doc = "Trigger overrun interrupt enabled"]
ENABLED,
}
impl OIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
OIEW::DISABLED => false,
OIEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _OIEW<'a> {
w: &'a mut W,
}
impl<'a> _OIEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Trigger overrun interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(OIEW::DISABLED)
}
#[doc = "Trigger overrun interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(OIEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 8);
self.w.bits |= ((value as u32) & 0x01) << 8;
self.w
}
}
#[doc = "Possible values of the field `GE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GER {
#[doc = "DMA request generation disabled"]
DISABLED,
#[doc = "DMA request enabled"]
ENABLED,
}
impl GER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
GER::DISABLED => false,
GER::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> GER {
match value {
false => GER::DISABLED,
true => GER::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == GER::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == GER::ENABLED
}
}
#[doc = "Values that can be written to the field `GE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GEW {
#[doc = "DMA request generation disabled"]
DISABLED,
#[doc = "DMA request enabled"]
ENABLED,
}
impl GEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
GEW::DISABLED => false,
GEW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _GEW<'a> {
w: &'a mut W,
}
impl<'a> _GEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA request generation disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(GEW::DISABLED)
}
#[doc = "DMA request enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(GEW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 16);
self.w.bits |= ((value as u32) & 0x01) << 16;
self.w
}
}
#[doc = "Possible values of the field `GPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GPOLR {
#[doc = "No event, i.e. no detection nor generation"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl GPOLR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
GPOLR::NOEDGE => 0,
GPOLR::RISINGEDGE => 0x01,
GPOLR::FALLINGEDGE => 0x02,
GPOLR::BOTHEDGES => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> GPOLR {
match value {
0 => GPOLR::NOEDGE,
1 => GPOLR::RISINGEDGE,
2 => GPOLR::FALLINGEDGE,
3 => GPOLR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `NOEDGE`"]
#[inline(always)]
pub fn is_no_edge(&self) -> bool {
*self == GPOLR::NOEDGE
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == GPOLR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == GPOLR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == GPOLR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `GPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum GPOLW {
#[doc = "No event, i.e. no detection nor generation"]
NOEDGE,
#[doc = "Rising edge"]
RISINGEDGE,
#[doc = "Falling edge"]
FALLINGEDGE,
#[doc = "Rising and falling edges"]
BOTHEDGES,
}
impl GPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
GPOLW::NOEDGE => 0,
GPOLW::RISINGEDGE => 1,
GPOLW::FALLINGEDGE => 2,
GPOLW::BOTHEDGES => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _GPOLW<'a> {
w: &'a mut W,
}
impl<'a> _GPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPOLW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "No event, i.e. no detection nor generation"]
#[inline(always)]
pub fn no_edge(self) -> &'a mut W {
self.variant(GPOLW::NOEDGE)
}
#[doc = "Rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(GPOLW::RISINGEDGE)
}
#[doc = "Falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(GPOLW::FALLINGEDGE)
}
#[doc = "Rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(GPOLW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 17);
self.w.bits |= ((value as u32) & 0x03) << 17;
self.w
}
}
#[doc = r"Value of the field"]
pub struct GNBREQR {
bits: u8,
}
impl GNBREQR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r"Proxy"]
pub struct _GNBREQW<'a> {
w: &'a mut W,
}
impl<'a> _GNBREQW<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x1f << 19);
self.w.bits |= ((value as u32) & 0x1f) << 19;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - DMA request trigger input selected"]
#[inline(always)]
pub fn sig_id(&self) -> SIG_IDR {
SIG_IDR::_from(((self.bits >> 0) & 0x1f) as u8)
}
#[doc = "Bit 8 - Interrupt enable at trigger event overrun"]
#[inline(always)]
pub fn oie(&self) -> OIER {
OIER::_from(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 16 - DMA request generator channel enable/disable"]
#[inline(always)]
pub fn ge(&self) -> GER {
GER::_from(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input"]
#[inline(always)]
pub fn gpol(&self) -> GPOLR {
GPOLR::_from(((self.bits >> 17) & 0x03) as u8)
}
#[doc = "Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset."]
#[inline(always)]
pub fn gnbreq(&self) -> GNBREQR {
let bits = ((self.bits >> 19) & 0x1f) as u8;
GNBREQR { bits }
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - DMA request trigger input selected"]
#[inline(always)]
pub fn sig_id(&mut self) -> _SIG_IDW {
_SIG_IDW { w: self }
}
#[doc = "Bit 8 - Interrupt enable at trigger event overrun"]
#[inline(always)]
pub fn oie(&mut self) -> _OIEW {
_OIEW { w: self }
}
#[doc = "Bit 16 - DMA request generator channel enable/disable"]
#[inline(always)]
pub fn ge(&mut self) -> _GEW {
_GEW { w: self }
}
#[doc = "Bits 17:18 - DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input"]
#[inline(always)]
pub fn gpol(&mut self) -> _GPOLW {
_GPOLW { w: self }
}
#[doc = "Bits 19:23 - Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset."]
#[inline(always)]
pub fn gnbreq(&mut self) -> _GNBREQW {
_GNBREQW { w: self }
}
}