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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::CR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0x7f } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Value of the field"] pub struct TR { bits: u8, } impl TR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _TW<'a> { w: &'a mut W, } impl<'a> _TW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x7f << 0); self.w.bits |= ((value as u32) & 0x7f) << 0; self.w } } #[doc = "Possible values of the field `WDGA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDGAR { #[doc = "Watchdog disabled"] DISABLED, #[doc = "Watchdog enabled"] ENABLED, } impl WDGAR { #[doc = r"Returns `true` if the bit is clear (0)"] #[inline(always)] pub fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = r"Returns `true` if the bit is set (1)"] #[inline(always)] pub fn bit_is_set(&self) -> bool { self.bit() } #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bit(&self) -> bool { match *self { WDGAR::DISABLED => false, WDGAR::ENABLED => true, } } #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _from(value: bool) -> WDGAR { match value { false => WDGAR::DISABLED, true => WDGAR::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == WDGAR::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == WDGAR::ENABLED } } #[doc = "Values that can be written to the field `WDGA`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum WDGAW { #[doc = "Watchdog disabled"] DISABLED, #[doc = "Watchdog enabled"] ENABLED, } impl WDGAW { #[allow(missing_docs)] #[doc(hidden)] #[inline(always)] pub fn _bits(&self) -> bool { match *self { WDGAW::DISABLED => false, WDGAW::ENABLED => true, } } } #[doc = r"Proxy"] pub struct _WDGAW<'a> { w: &'a mut W, } impl<'a> _WDGAW<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: WDGAW) -> &'a mut W { { self.bit(variant._bits()) } } #[doc = "Watchdog disabled"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(WDGAW::DISABLED) } #[doc = "Watchdog enabled"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(WDGAW::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(0x01 << 7); self.w.bits |= ((value as u32) & 0x01) << 7; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:6 - 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB\\[1:0\\]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)."] #[inline(always)] pub fn t(&self) -> TR { let bits = ((self.bits >> 0) & 0x7f) as u8; TR { bits } } #[doc = "Bit 7 - Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset."] #[inline(always)] pub fn wdga(&self) -> WDGAR { WDGAR::_from(((self.bits >> 7) & 0x01) != 0) } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:6 - 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB\\[1:0\\]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)."] #[inline(always)] pub fn t(&mut self) -> _TW { _TW { w: self } } #[doc = "Bit 7 - Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset."] #[inline(always)] pub fn wdga(&mut self) -> _WDGAW { _WDGAW { w: self } } }