#[doc = r"Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR {
#[doc = r"Modifies the contents of the register"]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
self.register.set(f(&R { bits }, &mut W { bits }).bits);
}
#[doc = r"Reads the contents of the register"]
#[inline(always)]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r"Writes to the register"]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
self.register.set(
f(&mut W {
bits: Self::reset_value(),
})
.bits,
);
}
#[doc = r"Reset value of the register"]
#[inline(always)]
pub const fn reset_value() -> u32 {
0
}
#[doc = r"Writes the reset value to the register"]
#[inline(always)]
pub fn reset(&self) {
self.register.set(Self::reset_value())
}
}
#[doc = "Possible values of the field `ENC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ENCR {
#[doc = "Encoder mode disabled"]
DISABLED,
#[doc = "Encoder mode enabled"]
ENABLED,
}
impl ENCR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
ENCR::DISABLED => false,
ENCR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> ENCR {
match value {
false => ENCR::DISABLED,
true => ENCR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ENCR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ENCR::ENABLED
}
}
#[doc = "Values that can be written to the field `ENC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ENCW {
#[doc = "Encoder mode disabled"]
DISABLED,
#[doc = "Encoder mode enabled"]
ENABLED,
}
impl ENCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
ENCW::DISABLED => false,
ENCW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _ENCW<'a> {
w: &'a mut W,
}
impl<'a> _ENCW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ENCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Encoder mode disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(ENCW::DISABLED)
}
#[doc = "Encoder mode enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(ENCW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 24);
self.w.bits |= ((value as u32) & 0x01) << 24;
self.w
}
}
#[doc = "Possible values of the field `COUNTMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COUNTMODER {
#[doc = "The counter is incremented following each internal clock pulse"]
INTERNAL,
#[doc = "The counter is incremented following each valid clock pulse on the LPTIM external Input1"]
EXTERNAL,
}
impl COUNTMODER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
COUNTMODER::INTERNAL => false,
COUNTMODER::EXTERNAL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> COUNTMODER {
match value {
false => COUNTMODER::INTERNAL,
true => COUNTMODER::EXTERNAL,
}
}
#[doc = "Checks if the value of the field is `INTERNAL`"]
#[inline(always)]
pub fn is_internal(&self) -> bool {
*self == COUNTMODER::INTERNAL
}
#[doc = "Checks if the value of the field is `EXTERNAL`"]
#[inline(always)]
pub fn is_external(&self) -> bool {
*self == COUNTMODER::EXTERNAL
}
}
#[doc = "Values that can be written to the field `COUNTMODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COUNTMODEW {
#[doc = "The counter is incremented following each internal clock pulse"]
INTERNAL,
#[doc = "The counter is incremented following each valid clock pulse on the LPTIM external Input1"]
EXTERNAL,
}
impl COUNTMODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
COUNTMODEW::INTERNAL => false,
COUNTMODEW::EXTERNAL => true,
}
}
}
#[doc = r"Proxy"]
pub struct _COUNTMODEW<'a> {
w: &'a mut W,
}
impl<'a> _COUNTMODEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: COUNTMODEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The counter is incremented following each internal clock pulse"]
#[inline(always)]
pub fn internal(self) -> &'a mut W {
self.variant(COUNTMODEW::INTERNAL)
}
#[doc = "The counter is incremented following each valid clock pulse on the LPTIM external Input1"]
#[inline(always)]
pub fn external(self) -> &'a mut W {
self.variant(COUNTMODEW::EXTERNAL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 23);
self.w.bits |= ((value as u32) & 0x01) << 23;
self.w
}
}
#[doc = "Possible values of the field `PRELOAD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PRELOADR {
#[doc = "Registers are updated after each APB bus write access"]
IMMEDIATE,
#[doc = "Registers are updated at the end of the current LPTIM period"]
ENDOFPERIOD,
}
impl PRELOADR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
PRELOADR::IMMEDIATE => false,
PRELOADR::ENDOFPERIOD => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> PRELOADR {
match value {
false => PRELOADR::IMMEDIATE,
true => PRELOADR::ENDOFPERIOD,
}
}
#[doc = "Checks if the value of the field is `IMMEDIATE`"]
#[inline(always)]
pub fn is_immediate(&self) -> bool {
*self == PRELOADR::IMMEDIATE
}
#[doc = "Checks if the value of the field is `ENDOFPERIOD`"]
#[inline(always)]
pub fn is_end_of_period(&self) -> bool {
*self == PRELOADR::ENDOFPERIOD
}
}
#[doc = "Values that can be written to the field `PRELOAD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PRELOADW {
#[doc = "Registers are updated after each APB bus write access"]
IMMEDIATE,
#[doc = "Registers are updated at the end of the current LPTIM period"]
ENDOFPERIOD,
}
impl PRELOADW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
PRELOADW::IMMEDIATE => false,
PRELOADW::ENDOFPERIOD => true,
}
}
}
#[doc = r"Proxy"]
pub struct _PRELOADW<'a> {
w: &'a mut W,
}
impl<'a> _PRELOADW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PRELOADW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Registers are updated after each APB bus write access"]
#[inline(always)]
pub fn immediate(self) -> &'a mut W {
self.variant(PRELOADW::IMMEDIATE)
}
#[doc = "Registers are updated at the end of the current LPTIM period"]
#[inline(always)]
pub fn end_of_period(self) -> &'a mut W {
self.variant(PRELOADW::ENDOFPERIOD)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 22);
self.w.bits |= ((value as u32) & 0x01) << 22;
self.w
}
}
#[doc = "Possible values of the field `WAVPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAVPOLR {
#[doc = "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers"]
POSITIVE,
#[doc = "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
NEGATIVE,
}
impl WAVPOLR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
WAVPOLR::POSITIVE => false,
WAVPOLR::NEGATIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> WAVPOLR {
match value {
false => WAVPOLR::POSITIVE,
true => WAVPOLR::NEGATIVE,
}
}
#[doc = "Checks if the value of the field is `POSITIVE`"]
#[inline(always)]
pub fn is_positive(&self) -> bool {
*self == WAVPOLR::POSITIVE
}
#[doc = "Checks if the value of the field is `NEGATIVE`"]
#[inline(always)]
pub fn is_negative(&self) -> bool {
*self == WAVPOLR::NEGATIVE
}
}
#[doc = "Values that can be written to the field `WAVPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAVPOLW {
#[doc = "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers"]
POSITIVE,
#[doc = "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
NEGATIVE,
}
impl WAVPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
WAVPOLW::POSITIVE => false,
WAVPOLW::NEGATIVE => true,
}
}
}
#[doc = r"Proxy"]
pub struct _WAVPOLW<'a> {
w: &'a mut W,
}
impl<'a> _WAVPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: WAVPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
pub fn positive(self) -> &'a mut W {
self.variant(WAVPOLW::POSITIVE)
}
#[doc = "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
pub fn negative(self) -> &'a mut W {
self.variant(WAVPOLW::NEGATIVE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 21);
self.w.bits |= ((value as u32) & 0x01) << 21;
self.w
}
}
#[doc = "Possible values of the field `WAVE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAVER {
#[doc = "Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)"]
INACTIVE,
#[doc = "Activate the Set-once mode"]
ACTIVE,
}
impl WAVER {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
WAVER::INACTIVE => false,
WAVER::ACTIVE => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> WAVER {
match value {
false => WAVER::INACTIVE,
true => WAVER::ACTIVE,
}
}
#[doc = "Checks if the value of the field is `INACTIVE`"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == WAVER::INACTIVE
}
#[doc = "Checks if the value of the field is `ACTIVE`"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == WAVER::ACTIVE
}
}
#[doc = "Values that can be written to the field `WAVE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAVEW {
#[doc = "Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)"]
INACTIVE,
#[doc = "Activate the Set-once mode"]
ACTIVE,
}
impl WAVEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
WAVEW::INACTIVE => false,
WAVEW::ACTIVE => true,
}
}
}
#[doc = r"Proxy"]
pub struct _WAVEW<'a> {
w: &'a mut W,
}
impl<'a> _WAVEW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: WAVEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)"]
#[inline(always)]
pub fn inactive(self) -> &'a mut W {
self.variant(WAVEW::INACTIVE)
}
#[doc = "Activate the Set-once mode"]
#[inline(always)]
pub fn active(self) -> &'a mut W {
self.variant(WAVEW::ACTIVE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 20);
self.w.bits |= ((value as u32) & 0x01) << 20;
self.w
}
}
#[doc = "Possible values of the field `TIMOUT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TIMOUTR {
#[doc = "A trigger event arriving when the timer is already started will be ignored"]
DISABLED,
#[doc = "A trigger event arriving when the timer is already started will reset and restart the counter"]
ENABLED,
}
impl TIMOUTR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
TIMOUTR::DISABLED => false,
TIMOUTR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> TIMOUTR {
match value {
false => TIMOUTR::DISABLED,
true => TIMOUTR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TIMOUTR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TIMOUTR::ENABLED
}
}
#[doc = "Values that can be written to the field `TIMOUT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TIMOUTW {
#[doc = "A trigger event arriving when the timer is already started will be ignored"]
DISABLED,
#[doc = "A trigger event arriving when the timer is already started will reset and restart the counter"]
ENABLED,
}
impl TIMOUTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
TIMOUTW::DISABLED => false,
TIMOUTW::ENABLED => true,
}
}
}
#[doc = r"Proxy"]
pub struct _TIMOUTW<'a> {
w: &'a mut W,
}
impl<'a> _TIMOUTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIMOUTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "A trigger event arriving when the timer is already started will be ignored"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(TIMOUTW::DISABLED)
}
#[doc = "A trigger event arriving when the timer is already started will reset and restart the counter"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(TIMOUTW::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 19);
self.w.bits |= ((value as u32) & 0x01) << 19;
self.w
}
}
#[doc = "Possible values of the field `TRIGEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGENR {
#[doc = "Software trigger (counting start is initiated by software)"]
SW,
#[doc = "Rising edge is the active edge"]
RISINGEDGE,
#[doc = "Falling edge is the active edge"]
FALLINGEDGE,
#[doc = "Both edges are active edges"]
BOTHEDGES,
}
impl TRIGENR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
TRIGENR::SW => 0,
TRIGENR::RISINGEDGE => 0x01,
TRIGENR::FALLINGEDGE => 0x02,
TRIGENR::BOTHEDGES => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> TRIGENR {
match value {
0 => TRIGENR::SW,
1 => TRIGENR::RISINGEDGE,
2 => TRIGENR::FALLINGEDGE,
3 => TRIGENR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `SW`"]
#[inline(always)]
pub fn is_sw(&self) -> bool {
*self == TRIGENR::SW
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == TRIGENR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == TRIGENR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == TRIGENR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `TRIGEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGENW {
#[doc = "Software trigger (counting start is initiated by software)"]
SW,
#[doc = "Rising edge is the active edge"]
RISINGEDGE,
#[doc = "Falling edge is the active edge"]
FALLINGEDGE,
#[doc = "Both edges are active edges"]
BOTHEDGES,
}
impl TRIGENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
TRIGENW::SW => 0,
TRIGENW::RISINGEDGE => 1,
TRIGENW::FALLINGEDGE => 2,
TRIGENW::BOTHEDGES => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _TRIGENW<'a> {
w: &'a mut W,
}
impl<'a> _TRIGENW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TRIGENW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Software trigger (counting start is initiated by software)"]
#[inline(always)]
pub fn sw(self) -> &'a mut W {
self.variant(TRIGENW::SW)
}
#[doc = "Rising edge is the active edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(TRIGENW::RISINGEDGE)
}
#[doc = "Falling edge is the active edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(TRIGENW::FALLINGEDGE)
}
#[doc = "Both edges are active edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(TRIGENW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 17);
self.w.bits |= ((value as u32) & 0x03) << 17;
self.w
}
}
#[doc = "Possible values of the field `TRIGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGSELR {
#[doc = "lptim_ext_trig0"]
TRIG0,
#[doc = "lptim_ext_trig1"]
TRIG1,
#[doc = "lptim_ext_trig2"]
TRIG2,
#[doc = "lptim_ext_trig3"]
TRIG3,
#[doc = "lptim_ext_trig4"]
TRIG4,
#[doc = "lptim_ext_trig5"]
TRIG5,
#[doc = "lptim_ext_trig6"]
TRIG6,
#[doc = "lptim_ext_trig7"]
TRIG7,
}
impl TRIGSELR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
TRIGSELR::TRIG0 => 0,
TRIGSELR::TRIG1 => 0x01,
TRIGSELR::TRIG2 => 0x02,
TRIGSELR::TRIG3 => 0x03,
TRIGSELR::TRIG4 => 0x04,
TRIGSELR::TRIG5 => 0x05,
TRIGSELR::TRIG6 => 0x06,
TRIGSELR::TRIG7 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> TRIGSELR {
match value {
0 => TRIGSELR::TRIG0,
1 => TRIGSELR::TRIG1,
2 => TRIGSELR::TRIG2,
3 => TRIGSELR::TRIG3,
4 => TRIGSELR::TRIG4,
5 => TRIGSELR::TRIG5,
6 => TRIGSELR::TRIG6,
7 => TRIGSELR::TRIG7,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TRIG0`"]
#[inline(always)]
pub fn is_trig0(&self) -> bool {
*self == TRIGSELR::TRIG0
}
#[doc = "Checks if the value of the field is `TRIG1`"]
#[inline(always)]
pub fn is_trig1(&self) -> bool {
*self == TRIGSELR::TRIG1
}
#[doc = "Checks if the value of the field is `TRIG2`"]
#[inline(always)]
pub fn is_trig2(&self) -> bool {
*self == TRIGSELR::TRIG2
}
#[doc = "Checks if the value of the field is `TRIG3`"]
#[inline(always)]
pub fn is_trig3(&self) -> bool {
*self == TRIGSELR::TRIG3
}
#[doc = "Checks if the value of the field is `TRIG4`"]
#[inline(always)]
pub fn is_trig4(&self) -> bool {
*self == TRIGSELR::TRIG4
}
#[doc = "Checks if the value of the field is `TRIG5`"]
#[inline(always)]
pub fn is_trig5(&self) -> bool {
*self == TRIGSELR::TRIG5
}
#[doc = "Checks if the value of the field is `TRIG6`"]
#[inline(always)]
pub fn is_trig6(&self) -> bool {
*self == TRIGSELR::TRIG6
}
#[doc = "Checks if the value of the field is `TRIG7`"]
#[inline(always)]
pub fn is_trig7(&self) -> bool {
*self == TRIGSELR::TRIG7
}
}
#[doc = "Values that can be written to the field `TRIGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIGSELW {
#[doc = "lptim_ext_trig0"]
TRIG0,
#[doc = "lptim_ext_trig1"]
TRIG1,
#[doc = "lptim_ext_trig2"]
TRIG2,
#[doc = "lptim_ext_trig3"]
TRIG3,
#[doc = "lptim_ext_trig4"]
TRIG4,
#[doc = "lptim_ext_trig5"]
TRIG5,
#[doc = "lptim_ext_trig6"]
TRIG6,
#[doc = "lptim_ext_trig7"]
TRIG7,
}
impl TRIGSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
TRIGSELW::TRIG0 => 0,
TRIGSELW::TRIG1 => 1,
TRIGSELW::TRIG2 => 2,
TRIGSELW::TRIG3 => 3,
TRIGSELW::TRIG4 => 4,
TRIGSELW::TRIG5 => 5,
TRIGSELW::TRIG6 => 6,
TRIGSELW::TRIG7 => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _TRIGSELW<'a> {
w: &'a mut W,
}
impl<'a> _TRIGSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TRIGSELW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "lptim_ext_trig0"]
#[inline(always)]
pub fn trig0(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG0)
}
#[doc = "lptim_ext_trig1"]
#[inline(always)]
pub fn trig1(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG1)
}
#[doc = "lptim_ext_trig2"]
#[inline(always)]
pub fn trig2(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG2)
}
#[doc = "lptim_ext_trig3"]
#[inline(always)]
pub fn trig3(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG3)
}
#[doc = "lptim_ext_trig4"]
#[inline(always)]
pub fn trig4(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG4)
}
#[doc = "lptim_ext_trig5"]
#[inline(always)]
pub fn trig5(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG5)
}
#[doc = "lptim_ext_trig6"]
#[inline(always)]
pub fn trig6(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG6)
}
#[doc = "lptim_ext_trig7"]
#[inline(always)]
pub fn trig7(self) -> &'a mut W {
self.variant(TRIGSELW::TRIG7)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 13);
self.w.bits |= ((value as u32) & 0x07) << 13;
self.w
}
}
#[doc = "Possible values of the field `PRESC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PRESCR {
#[doc = "/1"]
DIV1,
#[doc = "/2"]
DIV2,
#[doc = "/4"]
DIV4,
#[doc = "/8"]
DIV8,
#[doc = "/16"]
DIV16,
#[doc = "/32"]
DIV32,
#[doc = "/64"]
DIV64,
#[doc = "/128"]
DIV128,
}
impl PRESCR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
PRESCR::DIV1 => 0,
PRESCR::DIV2 => 0x01,
PRESCR::DIV4 => 0x02,
PRESCR::DIV8 => 0x03,
PRESCR::DIV16 => 0x04,
PRESCR::DIV32 => 0x05,
PRESCR::DIV64 => 0x06,
PRESCR::DIV128 => 0x07,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> PRESCR {
match value {
0 => PRESCR::DIV1,
1 => PRESCR::DIV2,
2 => PRESCR::DIV4,
3 => PRESCR::DIV8,
4 => PRESCR::DIV16,
5 => PRESCR::DIV32,
6 => PRESCR::DIV64,
7 => PRESCR::DIV128,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DIV1`"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == PRESCR::DIV1
}
#[doc = "Checks if the value of the field is `DIV2`"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == PRESCR::DIV2
}
#[doc = "Checks if the value of the field is `DIV4`"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == PRESCR::DIV4
}
#[doc = "Checks if the value of the field is `DIV8`"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == PRESCR::DIV8
}
#[doc = "Checks if the value of the field is `DIV16`"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == PRESCR::DIV16
}
#[doc = "Checks if the value of the field is `DIV32`"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == PRESCR::DIV32
}
#[doc = "Checks if the value of the field is `DIV64`"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == PRESCR::DIV64
}
#[doc = "Checks if the value of the field is `DIV128`"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == PRESCR::DIV128
}
}
#[doc = "Values that can be written to the field `PRESC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PRESCW {
#[doc = "/1"]
DIV1,
#[doc = "/2"]
DIV2,
#[doc = "/4"]
DIV4,
#[doc = "/8"]
DIV8,
#[doc = "/16"]
DIV16,
#[doc = "/32"]
DIV32,
#[doc = "/64"]
DIV64,
#[doc = "/128"]
DIV128,
}
impl PRESCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
PRESCW::DIV1 => 0,
PRESCW::DIV2 => 1,
PRESCW::DIV4 => 2,
PRESCW::DIV8 => 3,
PRESCW::DIV16 => 4,
PRESCW::DIV32 => 5,
PRESCW::DIV64 => 6,
PRESCW::DIV128 => 7,
}
}
}
#[doc = r"Proxy"]
pub struct _PRESCW<'a> {
w: &'a mut W,
}
impl<'a> _PRESCW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PRESCW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "/1"]
#[inline(always)]
pub fn div1(self) -> &'a mut W {
self.variant(PRESCW::DIV1)
}
#[doc = "/2"]
#[inline(always)]
pub fn div2(self) -> &'a mut W {
self.variant(PRESCW::DIV2)
}
#[doc = "/4"]
#[inline(always)]
pub fn div4(self) -> &'a mut W {
self.variant(PRESCW::DIV4)
}
#[doc = "/8"]
#[inline(always)]
pub fn div8(self) -> &'a mut W {
self.variant(PRESCW::DIV8)
}
#[doc = "/16"]
#[inline(always)]
pub fn div16(self) -> &'a mut W {
self.variant(PRESCW::DIV16)
}
#[doc = "/32"]
#[inline(always)]
pub fn div32(self) -> &'a mut W {
self.variant(PRESCW::DIV32)
}
#[doc = "/64"]
#[inline(always)]
pub fn div64(self) -> &'a mut W {
self.variant(PRESCW::DIV64)
}
#[doc = "/128"]
#[inline(always)]
pub fn div128(self) -> &'a mut W {
self.variant(PRESCW::DIV128)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x07 << 9);
self.w.bits |= ((value as u32) & 0x07) << 9;
self.w
}
}
#[doc = "Possible values of the field `TRGFLT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGFLTR {
#[doc = "Any trigger active level change is considered as a valid trigger"]
IMMEDIATE,
#[doc = "Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger"]
CLOCKS2,
#[doc = "Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger"]
CLOCKS4,
#[doc = "Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger"]
CLOCKS8,
}
impl TRGFLTR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
TRGFLTR::IMMEDIATE => 0,
TRGFLTR::CLOCKS2 => 0x01,
TRGFLTR::CLOCKS4 => 0x02,
TRGFLTR::CLOCKS8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> TRGFLTR {
match value {
0 => TRGFLTR::IMMEDIATE,
1 => TRGFLTR::CLOCKS2,
2 => TRGFLTR::CLOCKS4,
3 => TRGFLTR::CLOCKS8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `IMMEDIATE`"]
#[inline(always)]
pub fn is_immediate(&self) -> bool {
*self == TRGFLTR::IMMEDIATE
}
#[doc = "Checks if the value of the field is `CLOCKS2`"]
#[inline(always)]
pub fn is_clocks2(&self) -> bool {
*self == TRGFLTR::CLOCKS2
}
#[doc = "Checks if the value of the field is `CLOCKS4`"]
#[inline(always)]
pub fn is_clocks4(&self) -> bool {
*self == TRGFLTR::CLOCKS4
}
#[doc = "Checks if the value of the field is `CLOCKS8`"]
#[inline(always)]
pub fn is_clocks8(&self) -> bool {
*self == TRGFLTR::CLOCKS8
}
}
#[doc = "Values that can be written to the field `TRGFLT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGFLTW {
#[doc = "Any trigger active level change is considered as a valid trigger"]
IMMEDIATE,
#[doc = "Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger"]
CLOCKS2,
#[doc = "Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger"]
CLOCKS4,
#[doc = "Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger"]
CLOCKS8,
}
impl TRGFLTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
TRGFLTW::IMMEDIATE => 0,
TRGFLTW::CLOCKS2 => 1,
TRGFLTW::CLOCKS4 => 2,
TRGFLTW::CLOCKS8 => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _TRGFLTW<'a> {
w: &'a mut W,
}
impl<'a> _TRGFLTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TRGFLTW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Any trigger active level change is considered as a valid trigger"]
#[inline(always)]
pub fn immediate(self) -> &'a mut W {
self.variant(TRGFLTW::IMMEDIATE)
}
#[doc = "Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger"]
#[inline(always)]
pub fn clocks2(self) -> &'a mut W {
self.variant(TRGFLTW::CLOCKS2)
}
#[doc = "Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger"]
#[inline(always)]
pub fn clocks4(self) -> &'a mut W {
self.variant(TRGFLTW::CLOCKS4)
}
#[doc = "Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger"]
#[inline(always)]
pub fn clocks8(self) -> &'a mut W {
self.variant(TRGFLTW::CLOCKS8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 6);
self.w.bits |= ((value as u32) & 0x03) << 6;
self.w
}
}
#[doc = "Possible values of the field `CKFLT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKFLTR {
#[doc = "Any external clock signal level change is considered as a valid transition"]
IMMEDIATE,
#[doc = "External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition"]
CLOCKS2,
#[doc = "External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition"]
CLOCKS4,
#[doc = "External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition"]
CLOCKS8,
}
impl CKFLTR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CKFLTR::IMMEDIATE => 0,
CKFLTR::CLOCKS2 => 0x01,
CKFLTR::CLOCKS4 => 0x02,
CKFLTR::CLOCKS8 => 0x03,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CKFLTR {
match value {
0 => CKFLTR::IMMEDIATE,
1 => CKFLTR::CLOCKS2,
2 => CKFLTR::CLOCKS4,
3 => CKFLTR::CLOCKS8,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `IMMEDIATE`"]
#[inline(always)]
pub fn is_immediate(&self) -> bool {
*self == CKFLTR::IMMEDIATE
}
#[doc = "Checks if the value of the field is `CLOCKS2`"]
#[inline(always)]
pub fn is_clocks2(&self) -> bool {
*self == CKFLTR::CLOCKS2
}
#[doc = "Checks if the value of the field is `CLOCKS4`"]
#[inline(always)]
pub fn is_clocks4(&self) -> bool {
*self == CKFLTR::CLOCKS4
}
#[doc = "Checks if the value of the field is `CLOCKS8`"]
#[inline(always)]
pub fn is_clocks8(&self) -> bool {
*self == CKFLTR::CLOCKS8
}
}
#[doc = "Values that can be written to the field `CKFLT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKFLTW {
#[doc = "Any external clock signal level change is considered as a valid transition"]
IMMEDIATE,
#[doc = "External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition"]
CLOCKS2,
#[doc = "External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition"]
CLOCKS4,
#[doc = "External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition"]
CLOCKS8,
}
impl CKFLTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CKFLTW::IMMEDIATE => 0,
CKFLTW::CLOCKS2 => 1,
CKFLTW::CLOCKS4 => 2,
CKFLTW::CLOCKS8 => 3,
}
}
}
#[doc = r"Proxy"]
pub struct _CKFLTW<'a> {
w: &'a mut W,
}
impl<'a> _CKFLTW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CKFLTW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Any external clock signal level change is considered as a valid transition"]
#[inline(always)]
pub fn immediate(self) -> &'a mut W {
self.variant(CKFLTW::IMMEDIATE)
}
#[doc = "External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition"]
#[inline(always)]
pub fn clocks2(self) -> &'a mut W {
self.variant(CKFLTW::CLOCKS2)
}
#[doc = "External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition"]
#[inline(always)]
pub fn clocks4(self) -> &'a mut W {
self.variant(CKFLTW::CLOCKS4)
}
#[doc = "External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition"]
#[inline(always)]
pub fn clocks8(self) -> &'a mut W {
self.variant(CKFLTW::CLOCKS8)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 3);
self.w.bits |= ((value as u32) & 0x03) << 3;
self.w
}
}
#[doc = "Possible values of the field `CKPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKPOLR {
#[doc = "The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active."]
RISINGEDGE,
#[doc = "The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active."]
FALLINGEDGE,
#[doc = "Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active."]
BOTHEDGES,
#[doc = r"Reserved"]
_Reserved(u8),
}
impl CKPOLR {
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u8 {
match *self {
CKPOLR::RISINGEDGE => 0,
CKPOLR::FALLINGEDGE => 0x01,
CKPOLR::BOTHEDGES => 0x02,
CKPOLR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: u8) -> CKPOLR {
match value {
0 => CKPOLR::RISINGEDGE,
1 => CKPOLR::FALLINGEDGE,
2 => CKPOLR::BOTHEDGES,
i => CKPOLR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == CKPOLR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == CKPOLR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == CKPOLR::BOTHEDGES
}
}
#[doc = "Values that can be written to the field `CKPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKPOLW {
#[doc = "The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active."]
RISINGEDGE,
#[doc = "The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active."]
FALLINGEDGE,
#[doc = "Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active."]
BOTHEDGES,
}
impl CKPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> u8 {
match *self {
CKPOLW::RISINGEDGE => 0,
CKPOLW::FALLINGEDGE => 1,
CKPOLW::BOTHEDGES => 2,
}
}
}
#[doc = r"Proxy"]
pub struct _CKPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CKPOLW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CKPOLW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active."]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(CKPOLW::RISINGEDGE)
}
#[doc = "The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active."]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(CKPOLW::FALLINGEDGE)
}
#[doc = "Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active."]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(CKPOLW::BOTHEDGES)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits &= !(0x03 << 1);
self.w.bits |= ((value as u32) & 0x03) << 1;
self.w
}
}
#[doc = "Possible values of the field `CKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKSELR {
#[doc = "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)"]
INTERNAL,
#[doc = "LPTIM is clocked by an external clock source through the LPTIM external Input1"]
EXTERNAL,
}
impl CKSELR {
#[doc = r"Returns `true` if the bit is clear (0)"]
#[inline(always)]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r"Returns `true` if the bit is set (1)"]
#[inline(always)]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r"Value of the field as raw bits"]
#[inline(always)]
pub fn bit(&self) -> bool {
match *self {
CKSELR::INTERNAL => false,
CKSELR::EXTERNAL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _from(value: bool) -> CKSELR {
match value {
false => CKSELR::INTERNAL,
true => CKSELR::EXTERNAL,
}
}
#[doc = "Checks if the value of the field is `INTERNAL`"]
#[inline(always)]
pub fn is_internal(&self) -> bool {
*self == CKSELR::INTERNAL
}
#[doc = "Checks if the value of the field is `EXTERNAL`"]
#[inline(always)]
pub fn is_external(&self) -> bool {
*self == CKSELR::EXTERNAL
}
}
#[doc = "Values that can be written to the field `CKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CKSELW {
#[doc = "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)"]
INTERNAL,
#[doc = "LPTIM is clocked by an external clock source through the LPTIM external Input1"]
EXTERNAL,
}
impl CKSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline(always)]
pub fn _bits(&self) -> bool {
match *self {
CKSELW::INTERNAL => false,
CKSELW::EXTERNAL => true,
}
}
}
#[doc = r"Proxy"]
pub struct _CKSELW<'a> {
w: &'a mut W,
}
impl<'a> _CKSELW<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CKSELW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)"]
#[inline(always)]
pub fn internal(self) -> &'a mut W {
self.variant(CKSELW::INTERNAL)
}
#[doc = "LPTIM is clocked by an external clock source through the LPTIM external Input1"]
#[inline(always)]
pub fn external(self) -> &'a mut W {
self.variant(CKSELW::EXTERNAL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits &= !(0x01 << 0);
self.w.bits |= ((value as u32) & 0x01) << 0;
self.w
}
}
impl R {
#[doc = r"Value of the register as raw bits"]
#[inline(always)]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 24 - Encoder mode enable"]
#[inline(always)]
pub fn enc(&self) -> ENCR {
ENCR::_from(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 23 - counter mode enabled"]
#[inline(always)]
pub fn countmode(&self) -> COUNTMODER {
COUNTMODER::_from(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 22 - Registers update mode"]
#[inline(always)]
pub fn preload(&self) -> PRELOADR {
PRELOADR::_from(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 21 - Waveform shape polarity"]
#[inline(always)]
pub fn wavpol(&self) -> WAVPOLR {
WAVPOLR::_from(((self.bits >> 21) & 0x01) != 0)
}
#[doc = "Bit 20 - Waveform shape"]
#[inline(always)]
pub fn wave(&self) -> WAVER {
WAVER::_from(((self.bits >> 20) & 0x01) != 0)
}
#[doc = "Bit 19 - Timeout enable"]
#[inline(always)]
pub fn timout(&self) -> TIMOUTR {
TIMOUTR::_from(((self.bits >> 19) & 0x01) != 0)
}
#[doc = "Bits 17:18 - Trigger enable and polarity"]
#[inline(always)]
pub fn trigen(&self) -> TRIGENR {
TRIGENR::_from(((self.bits >> 17) & 0x03) as u8)
}
#[doc = "Bits 13:15 - Trigger selector"]
#[inline(always)]
pub fn trigsel(&self) -> TRIGSELR {
TRIGSELR::_from(((self.bits >> 13) & 0x07) as u8)
}
#[doc = "Bits 9:11 - Clock prescaler"]
#[inline(always)]
pub fn presc(&self) -> PRESCR {
PRESCR::_from(((self.bits >> 9) & 0x07) as u8)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger"]
#[inline(always)]
pub fn trgflt(&self) -> TRGFLTR {
TRGFLTR::_from(((self.bits >> 6) & 0x03) as u8)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock"]
#[inline(always)]
pub fn ckflt(&self) -> CKFLTR {
CKFLTR::_from(((self.bits >> 3) & 0x03) as u8)
}
#[doc = "Bits 1:2 - Clock Polarity"]
#[inline(always)]
pub fn ckpol(&self) -> CKPOLR {
CKPOLR::_from(((self.bits >> 1) & 0x03) as u8)
}
#[doc = "Bit 0 - Clock selector"]
#[inline(always)]
pub fn cksel(&self) -> CKSELR {
CKSELR::_from(((self.bits >> 0) & 0x01) != 0)
}
}
impl W {
#[doc = r"Writes raw bits to the register"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 24 - Encoder mode enable"]
#[inline(always)]
pub fn enc(&mut self) -> _ENCW {
_ENCW { w: self }
}
#[doc = "Bit 23 - counter mode enabled"]
#[inline(always)]
pub fn countmode(&mut self) -> _COUNTMODEW {
_COUNTMODEW { w: self }
}
#[doc = "Bit 22 - Registers update mode"]
#[inline(always)]
pub fn preload(&mut self) -> _PRELOADW {
_PRELOADW { w: self }
}
#[doc = "Bit 21 - Waveform shape polarity"]
#[inline(always)]
pub fn wavpol(&mut self) -> _WAVPOLW {
_WAVPOLW { w: self }
}
#[doc = "Bit 20 - Waveform shape"]
#[inline(always)]
pub fn wave(&mut self) -> _WAVEW {
_WAVEW { w: self }
}
#[doc = "Bit 19 - Timeout enable"]
#[inline(always)]
pub fn timout(&mut self) -> _TIMOUTW {
_TIMOUTW { w: self }
}
#[doc = "Bits 17:18 - Trigger enable and polarity"]
#[inline(always)]
pub fn trigen(&mut self) -> _TRIGENW {
_TRIGENW { w: self }
}
#[doc = "Bits 13:15 - Trigger selector"]
#[inline(always)]
pub fn trigsel(&mut self) -> _TRIGSELW {
_TRIGSELW { w: self }
}
#[doc = "Bits 9:11 - Clock prescaler"]
#[inline(always)]
pub fn presc(&mut self) -> _PRESCW {
_PRESCW { w: self }
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger"]
#[inline(always)]
pub fn trgflt(&mut self) -> _TRGFLTW {
_TRGFLTW { w: self }
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock"]
#[inline(always)]
pub fn ckflt(&mut self) -> _CKFLTW {
_CKFLTW { w: self }
}
#[doc = "Bits 1:2 - Clock Polarity"]
#[inline(always)]
pub fn ckpol(&mut self) -> _CKPOLW {
_CKPOLW { w: self }
}
#[doc = "Bit 0 - Clock selector"]
#[inline(always)]
pub fn cksel(&mut self) -> _CKSELW {
_CKSELW { w: self }
}
}