stm32h7/stm32h747cm7/sdmmc1/
dctrl.rs1#[doc = "Register `DCTRL` reader"]
2pub struct R(crate::R<DCTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DCTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DCTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DCTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DCTRL` writer"]
17pub struct W(crate::W<DCTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DCTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DCTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DCTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DTEN` reader - Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
38pub type DTEN_R = crate::BitReader<bool>;
39#[doc = "Field `DTEN` writer - Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
40pub type DTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
41#[doc = "Field `DTDIR` reader - Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
42pub type DTDIR_R = crate::BitReader<bool>;
43#[doc = "Field `DTDIR` writer - Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
44pub type DTDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
45#[doc = "Field `DTMODE` reader - Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
46pub type DTMODE_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `DTMODE` writer - Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
48pub type DTMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTRL_SPEC, u8, u8, 2, O>;
49#[doc = "Field `DBLOCKSIZE` reader - Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
50pub type DBLOCKSIZE_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `DBLOCKSIZE` writer - Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
52pub type DBLOCKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTRL_SPEC, u8, u8, 4, O>;
53#[doc = "Field `RWSTART` reader - Read wait start. If this bit is set, read wait operation starts."]
54pub type RWSTART_R = crate::BitReader<bool>;
55#[doc = "Field `RWSTART` writer - Read wait start. If this bit is set, read wait operation starts."]
56pub type RWSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
57#[doc = "Field `RWSTOP` reader - Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
58pub type RWSTOP_R = crate::BitReader<bool>;
59#[doc = "Field `RWSTOP` writer - Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
60pub type RWSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
61#[doc = "Field `RWMOD` reader - Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
62pub type RWMOD_R = crate::BitReader<bool>;
63#[doc = "Field `RWMOD` writer - Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
64pub type RWMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
65#[doc = "Field `SDIOEN` reader - SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
66pub type SDIOEN_R = crate::BitReader<bool>;
67#[doc = "Field `SDIOEN` writer - SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
68pub type SDIOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
69#[doc = "Field `BOOTACKEN` reader - Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
70pub type BOOTACKEN_R = crate::BitReader<bool>;
71#[doc = "Field `BOOTACKEN` writer - Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
72pub type BOOTACKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
73#[doc = "Field `FIFORST` reader - FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
74pub type FIFORST_R = crate::BitReader<bool>;
75#[doc = "Field `FIFORST` writer - FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
76pub type FIFORST_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTRL_SPEC, bool, O>;
77impl R {
78 #[doc = "Bit 0 - Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
79 #[inline(always)]
80 pub fn dten(&self) -> DTEN_R {
81 DTEN_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
84 #[inline(always)]
85 pub fn dtdir(&self) -> DTDIR_R {
86 DTDIR_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bits 2:3 - Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
89 #[inline(always)]
90 pub fn dtmode(&self) -> DTMODE_R {
91 DTMODE_R::new(((self.bits >> 2) & 3) as u8)
92 }
93 #[doc = "Bits 4:7 - Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
94 #[inline(always)]
95 pub fn dblocksize(&self) -> DBLOCKSIZE_R {
96 DBLOCKSIZE_R::new(((self.bits >> 4) & 0x0f) as u8)
97 }
98 #[doc = "Bit 8 - Read wait start. If this bit is set, read wait operation starts."]
99 #[inline(always)]
100 pub fn rwstart(&self) -> RWSTART_R {
101 RWSTART_R::new(((self.bits >> 8) & 1) != 0)
102 }
103 #[doc = "Bit 9 - Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
104 #[inline(always)]
105 pub fn rwstop(&self) -> RWSTOP_R {
106 RWSTOP_R::new(((self.bits >> 9) & 1) != 0)
107 }
108 #[doc = "Bit 10 - Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
109 #[inline(always)]
110 pub fn rwmod(&self) -> RWMOD_R {
111 RWMOD_R::new(((self.bits >> 10) & 1) != 0)
112 }
113 #[doc = "Bit 11 - SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
114 #[inline(always)]
115 pub fn sdioen(&self) -> SDIOEN_R {
116 SDIOEN_R::new(((self.bits >> 11) & 1) != 0)
117 }
118 #[doc = "Bit 12 - Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
119 #[inline(always)]
120 pub fn bootacken(&self) -> BOOTACKEN_R {
121 BOOTACKEN_R::new(((self.bits >> 12) & 1) != 0)
122 }
123 #[doc = "Bit 13 - FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
124 #[inline(always)]
125 pub fn fiforst(&self) -> FIFORST_R {
126 FIFORST_R::new(((self.bits >> 13) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
131 #[inline(always)]
132 pub fn dten(&mut self) -> DTEN_W<0> {
133 DTEN_W::new(self)
134 }
135 #[doc = "Bit 1 - Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
136 #[inline(always)]
137 pub fn dtdir(&mut self) -> DTDIR_W<1> {
138 DTDIR_W::new(self)
139 }
140 #[doc = "Bits 2:3 - Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
141 #[inline(always)]
142 pub fn dtmode(&mut self) -> DTMODE_W<2> {
143 DTMODE_W::new(self)
144 }
145 #[doc = "Bits 4:7 - Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
146 #[inline(always)]
147 pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<4> {
148 DBLOCKSIZE_W::new(self)
149 }
150 #[doc = "Bit 8 - Read wait start. If this bit is set, read wait operation starts."]
151 #[inline(always)]
152 pub fn rwstart(&mut self) -> RWSTART_W<8> {
153 RWSTART_W::new(self)
154 }
155 #[doc = "Bit 9 - Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
156 #[inline(always)]
157 pub fn rwstop(&mut self) -> RWSTOP_W<9> {
158 RWSTOP_W::new(self)
159 }
160 #[doc = "Bit 10 - Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
161 #[inline(always)]
162 pub fn rwmod(&mut self) -> RWMOD_W<10> {
163 RWMOD_W::new(self)
164 }
165 #[doc = "Bit 11 - SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
166 #[inline(always)]
167 pub fn sdioen(&mut self) -> SDIOEN_W<11> {
168 SDIOEN_W::new(self)
169 }
170 #[doc = "Bit 12 - Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
171 #[inline(always)]
172 pub fn bootacken(&mut self) -> BOOTACKEN_W<12> {
173 BOOTACKEN_W::new(self)
174 }
175 #[doc = "Bit 13 - FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
176 #[inline(always)]
177 pub fn fiforst(&mut self) -> FIFORST_W<13> {
178 FIFORST_W::new(self)
179 }
180 #[doc = "Writes raw bits to the register."]
181 #[inline(always)]
182 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183 self.0.bits(bits);
184 self
185 }
186}
187#[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM).\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctrl](index.html) module"]
188pub struct DCTRL_SPEC;
189impl crate::RegisterSpec for DCTRL_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [dctrl::R](R) reader structure"]
193impl crate::Readable for DCTRL_SPEC {
194 type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [dctrl::W](W) writer structure"]
197impl crate::Writable for DCTRL_SPEC {
198 type Writer = W;
199}
200#[doc = "`reset()` method sets DCTRL to value 0"]
201impl crate::Resettable for DCTRL_SPEC {
202 #[inline(always)]
203 fn reset_value() -> Self::Ux {
204 0
205 }
206}