pub struct R(_);
Expand description
Register BCR1
reader
Implementations
sourceimpl R
impl R
sourcepub fn mbken(&self) -> MBKEN_R
pub fn mbken(&self) -> MBKEN_R
Bit 0 - Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus.
sourcepub fn muxen(&self) -> MUXEN_R
pub fn muxen(&self) -> MUXEN_R
Bit 1 - Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:
sourcepub fn mtyp(&self) -> MTYP_R
pub fn mtyp(&self) -> MTYP_R
Bits 2:3 - Memory type These bits define the type of external memory attached to the corresponding memory bank:
sourcepub fn mwid(&self) -> MWID_R
pub fn mwid(&self) -> MWID_R
Bits 4:5 - Memory data bus width Defines the external memory device width, valid for all type of memories.
sourcepub fn faccen(&self) -> FACCEN_R
pub fn faccen(&self) -> FACCEN_R
Bit 6 - Flash access enable This bit enables NOR Flash memory access operations.
sourcepub fn bursten(&self) -> BURSTEN_R
pub fn bursten(&self) -> BURSTEN_R
Bit 8 - Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:
sourcepub fn waitpol(&self) -> WAITPOL_R
pub fn waitpol(&self) -> WAITPOL_R
Bit 9 - Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:
sourcepub fn waitcfg(&self) -> WAITCFG_R
pub fn waitcfg(&self) -> WAITCFG_R
Bit 11 - Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
sourcepub fn wren(&self) -> WREN_R
pub fn wren(&self) -> WREN_R
Bit 12 - Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:
sourcepub fn waiten(&self) -> WAITEN_R
pub fn waiten(&self) -> WAITEN_R
Bit 13 - Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode.
sourcepub fn extmod(&self) -> EXTMOD_R
pub fn extmod(&self) -> EXTMOD_R
Bit 14 - Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).
sourcepub fn asyncwait(&self) -> ASYNCWAIT_R
pub fn asyncwait(&self) -> ASYNCWAIT_R
Bit 15 - Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
sourcepub fn cpsize(&self) -> CPSIZE_R
pub fn cpsize(&self) -> CPSIZE_R
Bits 16:18 - CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved.
sourcepub fn cburstrw(&self) -> CBURSTRW_R
pub fn cburstrw(&self) -> CBURSTRW_R
Bit 19 - Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.
sourcepub fn cclken(&self) -> CCLKEN_R
pub fn cclken(&self) -> CCLKEN_R
Bit 20 - Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
sourcepub fn wfdis(&self) -> WFDIS_R
pub fn wfdis(&self) -> WFDIS_R
Bit 21 - Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register.
Methods from Deref<Target = R<BCR1_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more