stm32h7_staging/common/fdcan2/4c3a8e1f/
rxf1c.rs

1///Register `RXF1C` reader
2pub type R = crate::R<RXF1Crs>;
3///Register `RXF1C` writer
4pub type W = crate::W<RXF1Crs>;
5///Field `F1SA` reader - Rx FIFO 1 Start Address
6pub type F1SA_R = crate::FieldReader<u16>;
7///Field `F1SA` writer - Rx FIFO 1 Start Address
8pub type F1SA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
9///Field `F1S` reader - Rx FIFO 1 Size
10pub type F1S_R = crate::FieldReader;
11///Field `F1S` writer - Rx FIFO 1 Size
12pub type F1S_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
13///Field `F1WM` reader - Rx FIFO 1 Watermark
14pub type F1WM_R = crate::FieldReader;
15///Field `F1WM` writer - Rx FIFO 1 Watermark
16pub type F1WM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
17///Field `F1OM` reader - FIFO 1 operation mode
18pub type F1OM_R = crate::BitReader;
19///Field `F1OM` writer - FIFO 1 operation mode
20pub type F1OM_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    ///Bits 2:15 - Rx FIFO 1 Start Address
23    #[inline(always)]
24    pub fn f1sa(&self) -> F1SA_R {
25        F1SA_R::new(((self.bits >> 2) & 0x3fff) as u16)
26    }
27    ///Bits 16:22 - Rx FIFO 1 Size
28    #[inline(always)]
29    pub fn f1s(&self) -> F1S_R {
30        F1S_R::new(((self.bits >> 16) & 0x7f) as u8)
31    }
32    ///Bits 24:30 - Rx FIFO 1 Watermark
33    #[inline(always)]
34    pub fn f1wm(&self) -> F1WM_R {
35        F1WM_R::new(((self.bits >> 24) & 0x7f) as u8)
36    }
37    ///Bit 31 - FIFO 1 operation mode
38    #[inline(always)]
39    pub fn f1om(&self) -> F1OM_R {
40        F1OM_R::new(((self.bits >> 31) & 1) != 0)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("RXF1C")
46            .field("f1sa", &self.f1sa())
47            .field("f1s", &self.f1s())
48            .field("f1wm", &self.f1wm())
49            .field("f1om", &self.f1om())
50            .finish()
51    }
52}
53impl W {
54    ///Bits 2:15 - Rx FIFO 1 Start Address
55    #[inline(always)]
56    pub fn f1sa(&mut self) -> F1SA_W<RXF1Crs> {
57        F1SA_W::new(self, 2)
58    }
59    ///Bits 16:22 - Rx FIFO 1 Size
60    #[inline(always)]
61    pub fn f1s(&mut self) -> F1S_W<RXF1Crs> {
62        F1S_W::new(self, 16)
63    }
64    ///Bits 24:30 - Rx FIFO 1 Watermark
65    #[inline(always)]
66    pub fn f1wm(&mut self) -> F1WM_W<RXF1Crs> {
67        F1WM_W::new(self, 24)
68    }
69    ///Bit 31 - FIFO 1 operation mode
70    #[inline(always)]
71    pub fn f1om(&mut self) -> F1OM_W<RXF1Crs> {
72        F1OM_W::new(self, 31)
73    }
74}
75/**FDCAN Rx FIFO 1 Configuration Register
76
77You can [`read`](crate::Reg::read) this register and get [`rxf1c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
78pub struct RXF1Crs;
79impl crate::RegisterSpec for RXF1Crs {
80    type Ux = u32;
81}
82///`read()` method returns [`rxf1c::R`](R) reader structure
83impl crate::Readable for RXF1Crs {}
84///`write(|w| ..)` method takes [`rxf1c::W`](W) writer structure
85impl crate::Writable for RXF1Crs {
86    type Safety = crate::Unsafe;
87    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
89}
90///`reset()` method sets RXF1C to value 0
91impl crate::Resettable for RXF1Crs {
92    const RESET_VALUE: u32 = 0;
93}
stm32h7_staging/common/fdcan2/4c3a8e1f/rxf1c.rs

stm32h7_staging/common/fdcan2/4c3a8e1f/
rxf1c.rs
