stm32h7_staging/common/adc2/b07460bc/
pcsel.rs

1///Register `PCSEL` reader
2pub type R = crate::R<PCSELrs>;
3///Register `PCSEL` writer
4pub type W = crate::W<PCSELrs>;
5/**Channel x (VINP\[i\]) pre selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u32)]
11pub enum PCSEL {
12    ///0: Input channel x is not pre-selected
13    NotPreselected = 0,
14    ///1: Pre-select input channel x
15    Preselected = 1,
16}
17impl From<PCSEL> for u32 {
18    #[inline(always)]
19    fn from(variant: PCSEL) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for PCSEL {
24    type Ux = u32;
25}
26impl crate::IsEnum for PCSEL {}
27///Field `PCSEL` reader - Channel x (VINP\[i\]) pre selection
28pub type PCSEL_R = crate::FieldReader<PCSEL>;
29impl PCSEL_R {
30    ///Get enumerated values variant
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<PCSEL> {
33        match self.bits {
34            0 => Some(PCSEL::NotPreselected),
35            1 => Some(PCSEL::Preselected),
36            _ => None,
37        }
38    }
39    ///Input channel x is not pre-selected
40    #[inline(always)]
41    pub fn is_not_preselected(&self) -> bool {
42        *self == PCSEL::NotPreselected
43    }
44    ///Pre-select input channel x
45    #[inline(always)]
46    pub fn is_preselected(&self) -> bool {
47        *self == PCSEL::Preselected
48    }
49}
50///Field `PCSEL` writer - Channel x (VINP\[i\]) pre selection
51pub type PCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 20, PCSEL>;
52impl<'a, REG> PCSEL_W<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55    REG::Ux: From<u32>,
56{
57    ///Input channel x is not pre-selected
58    #[inline(always)]
59    pub fn not_preselected(self) -> &'a mut crate::W<REG> {
60        self.variant(PCSEL::NotPreselected)
61    }
62    ///Pre-select input channel x
63    #[inline(always)]
64    pub fn preselected(self) -> &'a mut crate::W<REG> {
65        self.variant(PCSEL::Preselected)
66    }
67}
68impl R {
69    ///Bits 0:19 - Channel x (VINP\[i\]) pre selection
70    #[inline(always)]
71    pub fn pcsel(&self) -> PCSEL_R {
72        PCSEL_R::new(self.bits & 0x000f_ffff)
73    }
74}
75impl core::fmt::Debug for R {
76    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
77        f.debug_struct("PCSEL").field("pcsel", &self.pcsel()).finish()
78    }
79}
80impl W {
81    ///Bits 0:19 - Channel x (VINP\[i\]) pre selection
82    #[inline(always)]
83    pub fn pcsel(&mut self) -> PCSEL_W<PCSELrs> {
84        PCSEL_W::new(self, 0)
85    }
86}
87/**ADC pre channel selection register
88
89You can [`read`](crate::Reg::read) this register and get [`pcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
90pub struct PCSELrs;
91impl crate::RegisterSpec for PCSELrs {
92    type Ux = u32;
93}
94///`read()` method returns [`pcsel::R`](R) reader structure
95impl crate::Readable for PCSELrs {}
96///`write(|w| ..)` method takes [`pcsel::W`](W) writer structure
97impl crate::Writable for PCSELrs {
98    type Safety = crate::Unsafe;
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
101}
102///`reset()` method sets PCSEL to value 0
103impl crate::Resettable for PCSELrs {
104    const RESET_VALUE: u32 = 0;
105}
stm32h7_staging/common/adc2/b07460bc/pcsel.rs

stm32h7_staging/common/adc2/b07460bc/
pcsel.rs
