stm32h7_staging/common/fmc/9b6cc98c/sdcmr.rs
1///Register `SDCMR` reader
2pub type R = crate::R<SDCMRrs>;
3///Register `SDCMR` writer
4pub type W = crate::W<SDCMRrs>;
5///Field `MODE` reader - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0.
6pub type MODE_R = crate::FieldReader;
7///Field `MODE` writer - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0.
8pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `CTB2` reader - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
10pub type CTB2_R = crate::BitReader;
11///Field `CTB2` writer - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
12pub type CTB2_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CTB1` reader - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
14pub type CTB1_R = crate::BitReader;
15///Field `CTB1` writer - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
16pub type CTB1_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `NRFS` reader - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ....
18pub type NRFS_R = crate::FieldReader;
19///Field `NRFS` writer - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ....
20pub type NRFS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21/**Field `MRD` reader - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\[13:0\]
22bits are also used to program the extended mode register for mobile SDRAM.*/
23pub type MRD_R = crate::FieldReader<u16>;
24/**Field `MRD` writer - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\[13:0\]
25bits are also used to program the extended mode register for mobile SDRAM.*/
26pub type MRD_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
27impl R {
28 ///Bits 0:2 - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0.
29 #[inline(always)]
30 pub fn mode(&self) -> MODE_R {
31 MODE_R::new((self.bits & 7) as u8)
32 }
33 ///Bit 3 - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
34 #[inline(always)]
35 pub fn ctb2(&self) -> CTB2_R {
36 CTB2_R::new(((self.bits >> 3) & 1) != 0)
37 }
38 ///Bit 4 - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
39 #[inline(always)]
40 pub fn ctb1(&self) -> CTB1_R {
41 CTB1_R::new(((self.bits >> 4) & 1) != 0)
42 }
43 ///Bits 5:8 - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ....
44 #[inline(always)]
45 pub fn nrfs(&self) -> NRFS_R {
46 NRFS_R::new(((self.bits >> 5) & 0x0f) as u8)
47 }
48 /**Bits 9:22 - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\[13:0\]
49bits are also used to program the extended mode register for mobile SDRAM.*/
50 #[inline(always)]
51 pub fn mrd(&self) -> MRD_R {
52 MRD_R::new(((self.bits >> 9) & 0x3fff) as u16)
53 }
54}
55impl core::fmt::Debug for R {
56 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57 f.debug_struct("SDCMR")
58 .field("mode", &self.mode())
59 .field("ctb2", &self.ctb2())
60 .field("ctb1", &self.ctb1())
61 .field("nrfs", &self.nrfs())
62 .field("mrd", &self.mrd())
63 .finish()
64 }
65}
66impl W {
67 ///Bits 0:2 - Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0.
68 #[inline(always)]
69 pub fn mode(&mut self) -> MODE_W<SDCMRrs> {
70 MODE_W::new(self, 0)
71 }
72 ///Bit 3 - Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
73 #[inline(always)]
74 pub fn ctb2(&mut self) -> CTB2_W<SDCMRrs> {
75 CTB2_W::new(self, 3)
76 }
77 ///Bit 4 - Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
78 #[inline(always)]
79 pub fn ctb1(&mut self) -> CTB1_W<SDCMRrs> {
80 CTB1_W::new(self, 4)
81 }
82 ///Bits 5:8 - Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ....
83 #[inline(always)]
84 pub fn nrfs(&mut self) -> NRFS_W<SDCMRrs> {
85 NRFS_W::new(self, 5)
86 }
87 /**Bits 9:22 - Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD\[13:0\]
88bits are also used to program the extended mode register for mobile SDRAM.*/
89 #[inline(always)]
90 pub fn mrd(&mut self) -> MRD_W<SDCMRrs> {
91 MRD_W::new(self, 9)
92 }
93}
94/**This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks.
95
96You can [`read`](crate::Reg::read) this register and get [`sdcmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdcmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
97pub struct SDCMRrs;
98impl crate::RegisterSpec for SDCMRrs {
99 type Ux = u32;
100}
101///`read()` method returns [`sdcmr::R`](R) reader structure
102impl crate::Readable for SDCMRrs {}
103///`write(|w| ..)` method takes [`sdcmr::W`](W) writer structure
104impl crate::Writable for SDCMRrs {
105 type Safety = crate::Unsafe;
106 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
108}
109///`reset()` method sets SDCMR to value 0
110impl crate::Resettable for SDCMRrs {
111 const RESET_VALUE: u32 = 0;
112}