stm32h5/stm32h562/tim1/
ccmr3_output.rs

1///Register `CCMR3_Output` reader
2pub type R = crate::R<CCMR3_OUTPUTrs>;
3///Register `CCMR3_Output` writer
4pub type W = crate::W<CCMR3_OUTPUTrs>;
5///Output compare %s clear enable
6pub use super::ccmr1_output::OC1CE;
7///Output compare %s fast enable
8pub use super::ccmr1_output::OC1FE;
9///Output compare %s mode
10pub use super::ccmr1_output::OC1M;
11///Output compare %s mode, bit 3
12pub use super::ccmr1_output::OC1M_3;
13///Output compare %s preload enable
14pub use super::ccmr1_output::OC1PE;
15///Field `OCCE(5-6)` reader - Output compare %s clear enable
16pub use super::ccmr1_output::OCCE_R;
17///Field `OCCE(5-6)` writer - Output compare %s clear enable
18pub use super::ccmr1_output::OCCE_W;
19///Field `OCFE(5-6)` reader - Output compare %s fast enable
20pub use super::ccmr1_output::OCFE_R;
21///Field `OCFE(5-6)` writer - Output compare %s fast enable
22pub use super::ccmr1_output::OCFE_W;
23///Field `OCM_3(5-6)` reader - Output compare %s mode, bit 3
24pub use super::ccmr1_output::OCM_3_R;
25///Field `OCM_3(5-6)` writer - Output compare %s mode, bit 3
26pub use super::ccmr1_output::OCM_3_W;
27///Field `OCM(5-6)` reader - Output compare %s mode
28pub use super::ccmr1_output::OCM_R;
29///Field `OCM(5-6)` writer - Output compare %s mode
30pub use super::ccmr1_output::OCM_W;
31///Field `OCPE(5-6)` reader - Output compare %s preload enable
32pub use super::ccmr1_output::OCPE_R;
33///Field `OCPE(5-6)` writer - Output compare %s preload enable
34pub use super::ccmr1_output::OCPE_W;
35impl R {
36    ///Output compare (5-6) fast enable
37    ///
38    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5FE` field.</div>
39    #[inline(always)]
40    pub fn ocfe(&self, n: u8) -> OCFE_R {
41        #[allow(clippy::no_effect)]
42        [(); 2][n as usize];
43        OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0)
44    }
45    ///Iterator for array of:
46    ///Output compare (5-6) fast enable
47    #[inline(always)]
48    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
49        (0..2).map(move |n| OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0))
50    }
51    ///Bit 2 - Output compare 5 fast enable
52    #[inline(always)]
53    pub fn oc5fe(&self) -> OCFE_R {
54        OCFE_R::new(((self.bits >> 2) & 1) != 0)
55    }
56    ///Bit 10 - Output compare 6 fast enable
57    #[inline(always)]
58    pub fn oc6fe(&self) -> OCFE_R {
59        OCFE_R::new(((self.bits >> 10) & 1) != 0)
60    }
61    ///Output compare (5-6) preload enable
62    ///
63    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5PE` field.</div>
64    #[inline(always)]
65    pub fn ocpe(&self, n: u8) -> OCPE_R {
66        #[allow(clippy::no_effect)]
67        [(); 2][n as usize];
68        OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Output compare (5-6) preload enable
72    #[inline(always)]
73    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
74        (0..2).map(move |n| OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0))
75    }
76    ///Bit 3 - Output compare 5 preload enable
77    #[inline(always)]
78    pub fn oc5pe(&self) -> OCPE_R {
79        OCPE_R::new(((self.bits >> 3) & 1) != 0)
80    }
81    ///Bit 11 - Output compare 6 preload enable
82    #[inline(always)]
83    pub fn oc6pe(&self) -> OCPE_R {
84        OCPE_R::new(((self.bits >> 11) & 1) != 0)
85    }
86    ///Output compare (5-6) mode
87    ///
88    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5M` field.</div>
89    #[inline(always)]
90    pub fn ocm(&self, n: u8) -> OCM_R {
91        #[allow(clippy::no_effect)]
92        [(); 2][n as usize];
93        OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8)
94    }
95    ///Iterator for array of:
96    ///Output compare (5-6) mode
97    #[inline(always)]
98    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
99        (0..2).map(move |n| OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8))
100    }
101    ///Bits 4:6 - Output compare 5 mode
102    #[inline(always)]
103    pub fn oc5m(&self) -> OCM_R {
104        OCM_R::new(((self.bits >> 4) & 7) as u8)
105    }
106    ///Bits 12:14 - Output compare 6 mode
107    #[inline(always)]
108    pub fn oc6m(&self) -> OCM_R {
109        OCM_R::new(((self.bits >> 12) & 7) as u8)
110    }
111    ///Output compare (5-6) clear enable
112    ///
113    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5CE` field.</div>
114    #[inline(always)]
115    pub fn occe(&self, n: u8) -> OCCE_R {
116        #[allow(clippy::no_effect)]
117        [(); 2][n as usize];
118        OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0)
119    }
120    ///Iterator for array of:
121    ///Output compare (5-6) clear enable
122    #[inline(always)]
123    pub fn occe_iter(&self) -> impl Iterator<Item = OCCE_R> + '_ {
124        (0..2).map(move |n| OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0))
125    }
126    ///Bit 7 - Output compare 5 clear enable
127    #[inline(always)]
128    pub fn oc5ce(&self) -> OCCE_R {
129        OCCE_R::new(((self.bits >> 7) & 1) != 0)
130    }
131    ///Bit 15 - Output compare 6 clear enable
132    #[inline(always)]
133    pub fn oc6ce(&self) -> OCCE_R {
134        OCCE_R::new(((self.bits >> 15) & 1) != 0)
135    }
136    ///Output compare (5-6) mode, bit 3
137    ///
138    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5M_3` field.</div>
139    #[inline(always)]
140    pub fn ocm_3(&self, n: u8) -> OCM_3_R {
141        #[allow(clippy::no_effect)]
142        [(); 2][n as usize];
143        OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0)
144    }
145    ///Iterator for array of:
146    ///Output compare (5-6) mode, bit 3
147    #[inline(always)]
148    pub fn ocm_3_iter(&self) -> impl Iterator<Item = OCM_3_R> + '_ {
149        (0..2).map(move |n| OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0))
150    }
151    ///Bit 16 - Output compare 5 mode, bit 3
152    #[inline(always)]
153    pub fn oc5m_3(&self) -> OCM_3_R {
154        OCM_3_R::new(((self.bits >> 16) & 1) != 0)
155    }
156    ///Bit 24 - Output compare 6 mode, bit 3
157    #[inline(always)]
158    pub fn oc6m_3(&self) -> OCM_3_R {
159        OCM_3_R::new(((self.bits >> 24) & 1) != 0)
160    }
161}
162impl core::fmt::Debug for R {
163    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
164        f.debug_struct("CCMR3_Output")
165            .field("oc5fe", &self.oc5fe())
166            .field("oc6fe", &self.oc6fe())
167            .field("oc5pe", &self.oc5pe())
168            .field("oc6pe", &self.oc6pe())
169            .field("oc5m", &self.oc5m())
170            .field("oc6m", &self.oc6m())
171            .field("oc5ce", &self.oc5ce())
172            .field("oc6ce", &self.oc6ce())
173            .field("oc5m_3", &self.oc5m_3())
174            .field("oc6m_3", &self.oc6m_3())
175            .finish()
176    }
177}
178impl W {
179    ///Output compare (5-6) fast enable
180    ///
181    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5FE` field.</div>
182    #[inline(always)]
183    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR3_OUTPUTrs> {
184        #[allow(clippy::no_effect)]
185        [(); 2][n as usize];
186        OCFE_W::new(self, n * 8 + 2)
187    }
188    ///Bit 2 - Output compare 5 fast enable
189    #[inline(always)]
190    pub fn oc5fe(&mut self) -> OCFE_W<CCMR3_OUTPUTrs> {
191        OCFE_W::new(self, 2)
192    }
193    ///Bit 10 - Output compare 6 fast enable
194    #[inline(always)]
195    pub fn oc6fe(&mut self) -> OCFE_W<CCMR3_OUTPUTrs> {
196        OCFE_W::new(self, 10)
197    }
198    ///Output compare (5-6) preload enable
199    ///
200    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5PE` field.</div>
201    #[inline(always)]
202    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR3_OUTPUTrs> {
203        #[allow(clippy::no_effect)]
204        [(); 2][n as usize];
205        OCPE_W::new(self, n * 8 + 3)
206    }
207    ///Bit 3 - Output compare 5 preload enable
208    #[inline(always)]
209    pub fn oc5pe(&mut self) -> OCPE_W<CCMR3_OUTPUTrs> {
210        OCPE_W::new(self, 3)
211    }
212    ///Bit 11 - Output compare 6 preload enable
213    #[inline(always)]
214    pub fn oc6pe(&mut self) -> OCPE_W<CCMR3_OUTPUTrs> {
215        OCPE_W::new(self, 11)
216    }
217    ///Output compare (5-6) mode
218    ///
219    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5M` field.</div>
220    #[inline(always)]
221    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR3_OUTPUTrs> {
222        #[allow(clippy::no_effect)]
223        [(); 2][n as usize];
224        OCM_W::new(self, n * 8 + 4)
225    }
226    ///Bits 4:6 - Output compare 5 mode
227    #[inline(always)]
228    pub fn oc5m(&mut self) -> OCM_W<CCMR3_OUTPUTrs> {
229        OCM_W::new(self, 4)
230    }
231    ///Bits 12:14 - Output compare 6 mode
232    #[inline(always)]
233    pub fn oc6m(&mut self) -> OCM_W<CCMR3_OUTPUTrs> {
234        OCM_W::new(self, 12)
235    }
236    ///Output compare (5-6) clear enable
237    ///
238    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5CE` field.</div>
239    #[inline(always)]
240    pub fn occe(&mut self, n: u8) -> OCCE_W<CCMR3_OUTPUTrs> {
241        #[allow(clippy::no_effect)]
242        [(); 2][n as usize];
243        OCCE_W::new(self, n * 8 + 7)
244    }
245    ///Bit 7 - Output compare 5 clear enable
246    #[inline(always)]
247    pub fn oc5ce(&mut self) -> OCCE_W<CCMR3_OUTPUTrs> {
248        OCCE_W::new(self, 7)
249    }
250    ///Bit 15 - Output compare 6 clear enable
251    #[inline(always)]
252    pub fn oc6ce(&mut self) -> OCCE_W<CCMR3_OUTPUTrs> {
253        OCCE_W::new(self, 15)
254    }
255    ///Output compare (5-6) mode, bit 3
256    ///
257    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC5M_3` field.</div>
258    #[inline(always)]
259    pub fn ocm_3(&mut self, n: u8) -> OCM_3_W<CCMR3_OUTPUTrs> {
260        #[allow(clippy::no_effect)]
261        [(); 2][n as usize];
262        OCM_3_W::new(self, n * 8 + 16)
263    }
264    ///Bit 16 - Output compare 5 mode, bit 3
265    #[inline(always)]
266    pub fn oc5m_3(&mut self) -> OCM_3_W<CCMR3_OUTPUTrs> {
267        OCM_3_W::new(self, 16)
268    }
269    ///Bit 24 - Output compare 6 mode, bit 3
270    #[inline(always)]
271    pub fn oc6m_3(&mut self) -> OCM_3_W<CCMR3_OUTPUTrs> {
272        OCM_3_W::new(self, 24)
273    }
274}
275/**TIM1 capture/compare mode register 3
276
277You can [`read`](crate::Reg::read) this register and get [`ccmr3_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr3_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
278
279See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H562.html#TIM1:CCMR3_Output)*/
280pub struct CCMR3_OUTPUTrs;
281impl crate::RegisterSpec for CCMR3_OUTPUTrs {
282    type Ux = u32;
283}
284///`read()` method returns [`ccmr3_output::R`](R) reader structure
285impl crate::Readable for CCMR3_OUTPUTrs {}
286///`write(|w| ..)` method takes [`ccmr3_output::W`](W) writer structure
287impl crate::Writable for CCMR3_OUTPUTrs {
288    type Safety = crate::Unsafe;
289}
290///`reset()` method sets CCMR3_Output to value 0
291impl crate::Resettable for CCMR3_OUTPUTrs {}
stm32h5/stm32h562/tim1/ccmr3_output.rs

stm32h5/stm32h562/tim1/
ccmr3_output.rs
