stm32h5/stm32h533/tim2/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5/**Selects tim_ti1\[15:0\] input
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum TI1SEL {
12    ///0: TIM1_CHx input selected
13    Selected = 0,
14}
15impl From<TI1SEL> for u8 {
16    #[inline(always)]
17    fn from(variant: TI1SEL) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for TI1SEL {
22    type Ux = u8;
23}
24impl crate::IsEnum for TI1SEL {}
25///Field `TI1SEL` reader - Selects tim_ti1\[15:0\] input
26pub type TI1SEL_R = crate::FieldReader<TI1SEL>;
27impl TI1SEL_R {
28    ///Get enumerated values variant
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<TI1SEL> {
31        match self.bits {
32            0 => Some(TI1SEL::Selected),
33            _ => None,
34        }
35    }
36    ///TIM1_CHx input selected
37    #[inline(always)]
38    pub fn is_selected(&self) -> bool {
39        *self == TI1SEL::Selected
40    }
41}
42///Field `TI1SEL` writer - Selects tim_ti1\[15:0\] input
43pub type TI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, TI1SEL>;
44impl<'a, REG> TI1SEL_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47    REG::Ux: From<u8>,
48{
49    ///TIM1_CHx input selected
50    #[inline(always)]
51    pub fn selected(self) -> &'a mut crate::W<REG> {
52        self.variant(TI1SEL::Selected)
53    }
54}
55///Field `TI2SEL` reader - Selects tim_ti2\[15:0\] input
56pub use TI1SEL_R as TI2SEL_R;
57///Field `TI3SEL` reader - Selects tim_ti3\[15:0\] input
58pub use TI1SEL_R as TI3SEL_R;
59///Field `TI4SEL` reader - Selects tim_ti4\[15:0\] input
60pub use TI1SEL_R as TI4SEL_R;
61///Field `TI2SEL` writer - Selects tim_ti2\[15:0\] input
62pub use TI1SEL_W as TI2SEL_W;
63///Field `TI3SEL` writer - Selects tim_ti3\[15:0\] input
64pub use TI1SEL_W as TI3SEL_W;
65///Field `TI4SEL` writer - Selects tim_ti4\[15:0\] input
66pub use TI1SEL_W as TI4SEL_W;
67impl R {
68    ///Bits 0:3 - Selects tim_ti1\[15:0\] input
69    #[inline(always)]
70    pub fn ti1sel(&self) -> TI1SEL_R {
71        TI1SEL_R::new((self.bits & 0x0f) as u8)
72    }
73    ///Bits 8:11 - Selects tim_ti2\[15:0\] input
74    #[inline(always)]
75    pub fn ti2sel(&self) -> TI2SEL_R {
76        TI2SEL_R::new(((self.bits >> 8) & 0x0f) as u8)
77    }
78    ///Bits 16:19 - Selects tim_ti3\[15:0\] input
79    #[inline(always)]
80    pub fn ti3sel(&self) -> TI3SEL_R {
81        TI3SEL_R::new(((self.bits >> 16) & 0x0f) as u8)
82    }
83    ///Bits 24:27 - Selects tim_ti4\[15:0\] input
84    #[inline(always)]
85    pub fn ti4sel(&self) -> TI4SEL_R {
86        TI4SEL_R::new(((self.bits >> 24) & 0x0f) as u8)
87    }
88}
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("TISEL")
92            .field("ti1sel", &self.ti1sel())
93            .field("ti2sel", &self.ti2sel())
94            .field("ti3sel", &self.ti3sel())
95            .field("ti4sel", &self.ti4sel())
96            .finish()
97    }
98}
99impl W {
100    ///Bits 0:3 - Selects tim_ti1\[15:0\] input
101    #[inline(always)]
102    pub fn ti1sel(&mut self) -> TI1SEL_W<TISELrs> {
103        TI1SEL_W::new(self, 0)
104    }
105    ///Bits 8:11 - Selects tim_ti2\[15:0\] input
106    #[inline(always)]
107    pub fn ti2sel(&mut self) -> TI2SEL_W<TISELrs> {
108        TI2SEL_W::new(self, 8)
109    }
110    ///Bits 16:19 - Selects tim_ti3\[15:0\] input
111    #[inline(always)]
112    pub fn ti3sel(&mut self) -> TI3SEL_W<TISELrs> {
113        TI3SEL_W::new(self, 16)
114    }
115    ///Bits 24:27 - Selects tim_ti4\[15:0\] input
116    #[inline(always)]
117    pub fn ti4sel(&mut self) -> TI4SEL_W<TISELrs> {
118        TI4SEL_W::new(self, 24)
119    }
120}
121/**TIM2 timer input selection register
122
123You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
124
125See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H533.html#TIM2:TISEL)*/
126pub struct TISELrs;
127impl crate::RegisterSpec for TISELrs {
128    type Ux = u32;
129}
130///`read()` method returns [`tisel::R`](R) reader structure
131impl crate::Readable for TISELrs {}
132///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
133impl crate::Writable for TISELrs {
134    type Safety = crate::Unsafe;
135}
136///`reset()` method sets TISEL to value 0
137impl crate::Resettable for TISELrs {}
stm32h5/stm32h533/tim2/tisel.rs

stm32h5/stm32h533/tim2/
tisel.rs
