stm32h5/stm32h573/i2c1/
oar1.rs

1///Register `OAR1` reader
2pub type R = crate::R<OAR1rs>;
3///Register `OAR1` writer
4pub type W = crate::W<OAR1rs>;
5///Field `OA1` reader - Interface own slave address 7-bit addressing mode: OA1\[7:1\] contains the 7-bit own slave address. The bits OA1\[9\], OA1\[8\] and OA1\[0\] are don't care. 10-bit addressing mode: OA1\[9:0\] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
6pub type OA1_R = crate::FieldReader<u16>;
7///Field `OA1` writer - Interface own slave address 7-bit addressing mode: OA1\[7:1\] contains the 7-bit own slave address. The bits OA1\[9\], OA1\[8\] and OA1\[0\] are don't care. 10-bit addressing mode: OA1\[9:0\] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
8pub type OA1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16, crate::Safe>;
9/**Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum OA1MODE {
15    ///0: Own address 1 is a 7-bit address
16    Bit7 = 0,
17    ///1: Own address 1 is a 10-bit address
18    Bit10 = 1,
19}
20impl From<OA1MODE> for bool {
21    #[inline(always)]
22    fn from(variant: OA1MODE) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `OA1MODE` reader - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
27pub type OA1MODE_R = crate::BitReader<OA1MODE>;
28impl OA1MODE_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> OA1MODE {
32        match self.bits {
33            false => OA1MODE::Bit7,
34            true => OA1MODE::Bit10,
35        }
36    }
37    ///Own address 1 is a 7-bit address
38    #[inline(always)]
39    pub fn is_bit7(&self) -> bool {
40        *self == OA1MODE::Bit7
41    }
42    ///Own address 1 is a 10-bit address
43    #[inline(always)]
44    pub fn is_bit10(&self) -> bool {
45        *self == OA1MODE::Bit10
46    }
47}
48///Field `OA1MODE` writer - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
49pub type OA1MODE_W<'a, REG> = crate::BitWriter<'a, REG, OA1MODE>;
50impl<'a, REG> OA1MODE_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Own address 1 is a 7-bit address
55    #[inline(always)]
56    pub fn bit7(self) -> &'a mut crate::W<REG> {
57        self.variant(OA1MODE::Bit7)
58    }
59    ///Own address 1 is a 10-bit address
60    #[inline(always)]
61    pub fn bit10(self) -> &'a mut crate::W<REG> {
62        self.variant(OA1MODE::Bit10)
63    }
64}
65/**Own Address 1 enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum OA1EN {
71    ///0: Own address 1 disabled. The received slave address OA1 is NACKed
72    Disabled = 0,
73    ///1: Own address 1 enabled. The received slave address OA1 is ACKed
74    Enabled = 1,
75}
76impl From<OA1EN> for bool {
77    #[inline(always)]
78    fn from(variant: OA1EN) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `OA1EN` reader - Own Address 1 enable
83pub type OA1EN_R = crate::BitReader<OA1EN>;
84impl OA1EN_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> OA1EN {
88        match self.bits {
89            false => OA1EN::Disabled,
90            true => OA1EN::Enabled,
91        }
92    }
93    ///Own address 1 disabled. The received slave address OA1 is NACKed
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == OA1EN::Disabled
97    }
98    ///Own address 1 enabled. The received slave address OA1 is ACKed
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == OA1EN::Enabled
102    }
103}
104///Field `OA1EN` writer - Own Address 1 enable
105pub type OA1EN_W<'a, REG> = crate::BitWriter<'a, REG, OA1EN>;
106impl<'a, REG> OA1EN_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Own address 1 disabled. The received slave address OA1 is NACKed
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(OA1EN::Disabled)
114    }
115    ///Own address 1 enabled. The received slave address OA1 is ACKed
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(OA1EN::Enabled)
119    }
120}
121impl R {
122    ///Bits 0:9 - Interface own slave address 7-bit addressing mode: OA1\[7:1\] contains the 7-bit own slave address. The bits OA1\[9\], OA1\[8\] and OA1\[0\] are don't care. 10-bit addressing mode: OA1\[9:0\] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
123    #[inline(always)]
124    pub fn oa1(&self) -> OA1_R {
125        OA1_R::new((self.bits & 0x03ff) as u16)
126    }
127    ///Bit 10 - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
128    #[inline(always)]
129    pub fn oa1mode(&self) -> OA1MODE_R {
130        OA1MODE_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 15 - Own Address 1 enable
133    #[inline(always)]
134    pub fn oa1en(&self) -> OA1EN_R {
135        OA1EN_R::new(((self.bits >> 15) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("OAR1")
141            .field("oa1", &self.oa1())
142            .field("oa1mode", &self.oa1mode())
143            .field("oa1en", &self.oa1en())
144            .finish()
145    }
146}
147impl W {
148    ///Bits 0:9 - Interface own slave address 7-bit addressing mode: OA1\[7:1\] contains the 7-bit own slave address. The bits OA1\[9\], OA1\[8\] and OA1\[0\] are don't care. 10-bit addressing mode: OA1\[9:0\] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
149    #[inline(always)]
150    pub fn oa1(&mut self) -> OA1_W<OAR1rs> {
151        OA1_W::new(self, 0)
152    }
153    ///Bit 10 - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
154    #[inline(always)]
155    pub fn oa1mode(&mut self) -> OA1MODE_W<OAR1rs> {
156        OA1MODE_W::new(self, 10)
157    }
158    ///Bit 15 - Own Address 1 enable
159    #[inline(always)]
160    pub fn oa1en(&mut self) -> OA1EN_W<OAR1rs> {
161        OA1EN_W::new(self, 15)
162    }
163}
164/**I2C own address 1 register
165
166You can [`read`](crate::Reg::read) this register and get [`oar1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32H573.html#I2C1:OAR1)*/
169pub struct OAR1rs;
170impl crate::RegisterSpec for OAR1rs {
171    type Ux = u32;
172}
173///`read()` method returns [`oar1::R`](R) reader structure
174impl crate::Readable for OAR1rs {}
175///`write(|w| ..)` method takes [`oar1::W`](W) writer structure
176impl crate::Writable for OAR1rs {
177    type Safety = crate::Unsafe;
178}
179///`reset()` method sets OAR1 to value 0
180impl crate::Resettable for OAR1rs {}
stm32h5/stm32h573/i2c1/oar1.rs

stm32h5/stm32h573/i2c1/
oar1.rs
