Module tisel 

TIM1 timer input selection register

Re-exports

pub use TI1SEL_R as TI2SEL_R;

pub use TI1SEL_R as TI3SEL_R;

pub use TI1SEL_R as TI4SEL_R;

pub use TI1SEL_W as TI2SEL_W;

pub use TI1SEL_W as TI3SEL_W;

pub use TI1SEL_W as TI4SEL_W;

Structs

TISELrs

TIM1 timer input selection register

Enums

TI1SEL

Selects tim_ti1[0..15] input … Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list.

Type Aliases

R

Register TISEL reader

TI1SEL_R

Field TI1SEL reader - Selects tim_ti1[0..15] input … Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list.

TI1SEL_W

Field TI1SEL writer - Selects tim_ti1[0..15] input … Refer to Section 65.3.2: TIM1 pins and internal signals for interconnects list.

W

Register TISEL writer