#[repr(u8)]
pub enum PLLQ_A {
Div2,
Div4,
Div6,
Div8,
}
Expand description
Main PLL division factor for PLLUSB1CLK(48 MHz clock)
Value on reset: 0
Variants
Div2
0: pll_q_ck = vco_ck / 2
Div4
1: pll_q_ck = vco_ck / 4
Div6
2: pll_q_ck = vco_ck / 6
Div8
3: pll_q_ck = vco_ck / 8
Trait Implementations
impl Copy for PLLQ_A
impl StructuralPartialEq for PLLQ_A
Auto Trait Implementations
impl RefUnwindSafe for PLLQ_A
impl Send for PLLQ_A
impl Sync for PLLQ_A
impl Unpin for PLLQ_A
impl UnwindSafe for PLLQ_A
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more