stm32g4/stm32g431/tim1/
dtr2.rs

1///Register `DTR2` reader
2pub type R = crate::R<DTR2rs>;
3///Register `DTR2` writer
4pub type W = crate::W<DTR2rs>;
5///Field `DTGF` reader - Dead-time falling edge generator setup
6pub type DTGF_R = crate::FieldReader;
7///Field `DTGF` writer - Dead-time falling edge generator setup
8pub type DTGF_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9///Field `DTAE` reader - Deadtime Asymmetric Enable
10pub type DTAE_R = crate::BitReader;
11///Field `DTAE` writer - Deadtime Asymmetric Enable
12pub type DTAE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DTPE` reader - Deadtime Preload Enable
14pub type DTPE_R = crate::BitReader;
15///Field `DTPE` writer - Deadtime Preload Enable
16pub type DTPE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bits 0:7 - Dead-time falling edge generator setup
19    #[inline(always)]
20    pub fn dtgf(&self) -> DTGF_R {
21        DTGF_R::new((self.bits & 0xff) as u8)
22    }
23    ///Bit 16 - Deadtime Asymmetric Enable
24    #[inline(always)]
25    pub fn dtae(&self) -> DTAE_R {
26        DTAE_R::new(((self.bits >> 16) & 1) != 0)
27    }
28    ///Bit 17 - Deadtime Preload Enable
29    #[inline(always)]
30    pub fn dtpe(&self) -> DTPE_R {
31        DTPE_R::new(((self.bits >> 17) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("DTR2")
37            .field("dtpe", &self.dtpe())
38            .field("dtae", &self.dtae())
39            .field("dtgf", &self.dtgf())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:7 - Dead-time falling edge generator setup
45    #[inline(always)]
46    pub fn dtgf(&mut self) -> DTGF_W<DTR2rs> {
47        DTGF_W::new(self, 0)
48    }
49    ///Bit 16 - Deadtime Asymmetric Enable
50    #[inline(always)]
51    pub fn dtae(&mut self) -> DTAE_W<DTR2rs> {
52        DTAE_W::new(self, 16)
53    }
54    ///Bit 17 - Deadtime Preload Enable
55    #[inline(always)]
56    pub fn dtpe(&mut self) -> DTPE_W<DTR2rs> {
57        DTPE_W::new(self, 17)
58    }
59}
60/**timer Deadtime Register 2
61
62You can [`read`](crate::Reg::read) this register and get [`dtr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM1:DTR2)*/
65pub struct DTR2rs;
66impl crate::RegisterSpec for DTR2rs {
67    type Ux = u32;
68}
69///`read()` method returns [`dtr2::R`](R) reader structure
70impl crate::Readable for DTR2rs {}
71///`write(|w| ..)` method takes [`dtr2::W`](W) writer structure
72impl crate::Writable for DTR2rs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets DTR2 to value 0
76impl crate::Resettable for DTR2rs {}
stm32g4/stm32g431/tim1/dtr2.rs

stm32g4/stm32g431/tim1/
dtr2.rs
