stm32g4/stm32g484/tim1/
af2.rs

1///Register `AF2` reader
2pub type R = crate::R<AF2rs>;
3///Register `AF2` writer
4pub type W = crate::W<AF2rs>;
5///Field `BKINE` reader - BRK BKIN input enable
6pub type BKINE_R = crate::BitReader;
7///Field `BKINE` writer - BRK BKIN input enable
8pub type BKINE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `BK2CMP1E` reader - BRK2 COMP1 enable
10pub type BK2CMP1E_R = crate::BitReader;
11///Field `BK2CMP1E` writer - BRK2 COMP1 enable
12pub type BK2CMP1E_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `BK2CMP2E` reader - BRK2 COMP2 enable
14pub type BK2CMP2E_R = crate::BitReader;
15///Field `BK2CMP2E` writer - BRK2 COMP2 enable
16pub type BK2CMP2E_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `BK2CMP3E` reader - BRK2 COMP3 enable
18pub type BK2CMP3E_R = crate::BitReader;
19///Field `BK2CMP3E` writer - BRK2 COMP3 enable
20pub type BK2CMP3E_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `BK2CMP4E` reader - BRK2 COMP4 enable
22pub type BK2CMP4E_R = crate::BitReader;
23///Field `BK2CMP4E` writer - BRK2 COMP4 enable
24pub type BK2CMP4E_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `BK2CMP5E` reader - BRK2 COMP5 enable
26pub type BK2CMP5E_R = crate::BitReader;
27///Field `BK2CMP5E` writer - BRK2 COMP5 enable
28pub type BK2CMP5E_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `BK2CMP6E` reader - BRK2 COMP6 enable
30pub type BK2CMP6E_R = crate::BitReader;
31///Field `BK2CMP6E` writer - BRK2 COMP6 enable
32pub type BK2CMP6E_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `BK2CMP7E` reader - BRK2 COMP7 enable
34pub type BK2CMP7E_R = crate::BitReader;
35///Field `BK2CMP7E` writer - BRK2 COMP7 enable
36pub type BK2CMP7E_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `BK2INP` reader - BRK2 BKIN input polarity
38pub type BK2INP_R = crate::BitReader;
39///Field `BK2INP` writer - BRK2 BKIN input polarity
40pub type BK2INP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `BK2CMP1P` reader - BRK2 COMP1 input polarity
42pub type BK2CMP1P_R = crate::BitReader;
43///Field `BK2CMP1P` writer - BRK2 COMP1 input polarity
44pub type BK2CMP1P_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `BK2CMP2P` reader - BRK2 COMP2 input polarity
46pub type BK2CMP2P_R = crate::BitReader;
47///Field `BK2CMP2P` writer - BRK2 COMP2 input polarity
48pub type BK2CMP2P_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `BK2CMP3P` reader - BRK2 COMP3 input polarity
50pub type BK2CMP3P_R = crate::BitReader;
51///Field `BK2CMP3P` writer - BRK2 COMP3 input polarity
52pub type BK2CMP3P_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `BK2CMP4P` reader - BRK2 COMP4 input polarity
54pub type BK2CMP4P_R = crate::BitReader;
55///Field `BK2CMP4P` writer - BRK2 COMP4 input polarity
56pub type BK2CMP4P_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `OCRSEL` reader - OCREF_CLR source selection
58pub type OCRSEL_R = crate::FieldReader;
59///Field `OCRSEL` writer - OCREF_CLR source selection
60pub type OCRSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
61impl R {
62    ///Bit 0 - BRK BKIN input enable
63    #[inline(always)]
64    pub fn bkine(&self) -> BKINE_R {
65        BKINE_R::new((self.bits & 1) != 0)
66    }
67    ///Bit 1 - BRK2 COMP1 enable
68    #[inline(always)]
69    pub fn bk2cmp1e(&self) -> BK2CMP1E_R {
70        BK2CMP1E_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    ///Bit 2 - BRK2 COMP2 enable
73    #[inline(always)]
74    pub fn bk2cmp2e(&self) -> BK2CMP2E_R {
75        BK2CMP2E_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    ///Bit 3 - BRK2 COMP3 enable
78    #[inline(always)]
79    pub fn bk2cmp3e(&self) -> BK2CMP3E_R {
80        BK2CMP3E_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    ///Bit 4 - BRK2 COMP4 enable
83    #[inline(always)]
84    pub fn bk2cmp4e(&self) -> BK2CMP4E_R {
85        BK2CMP4E_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    ///Bit 5 - BRK2 COMP5 enable
88    #[inline(always)]
89    pub fn bk2cmp5e(&self) -> BK2CMP5E_R {
90        BK2CMP5E_R::new(((self.bits >> 5) & 1) != 0)
91    }
92    ///Bit 6 - BRK2 COMP6 enable
93    #[inline(always)]
94    pub fn bk2cmp6e(&self) -> BK2CMP6E_R {
95        BK2CMP6E_R::new(((self.bits >> 6) & 1) != 0)
96    }
97    ///Bit 7 - BRK2 COMP7 enable
98    #[inline(always)]
99    pub fn bk2cmp7e(&self) -> BK2CMP7E_R {
100        BK2CMP7E_R::new(((self.bits >> 7) & 1) != 0)
101    }
102    ///Bit 9 - BRK2 BKIN input polarity
103    #[inline(always)]
104    pub fn bk2inp(&self) -> BK2INP_R {
105        BK2INP_R::new(((self.bits >> 9) & 1) != 0)
106    }
107    ///Bit 10 - BRK2 COMP1 input polarity
108    #[inline(always)]
109    pub fn bk2cmp1p(&self) -> BK2CMP1P_R {
110        BK2CMP1P_R::new(((self.bits >> 10) & 1) != 0)
111    }
112    ///Bit 11 - BRK2 COMP2 input polarity
113    #[inline(always)]
114    pub fn bk2cmp2p(&self) -> BK2CMP2P_R {
115        BK2CMP2P_R::new(((self.bits >> 11) & 1) != 0)
116    }
117    ///Bit 12 - BRK2 COMP3 input polarity
118    #[inline(always)]
119    pub fn bk2cmp3p(&self) -> BK2CMP3P_R {
120        BK2CMP3P_R::new(((self.bits >> 12) & 1) != 0)
121    }
122    ///Bit 13 - BRK2 COMP4 input polarity
123    #[inline(always)]
124    pub fn bk2cmp4p(&self) -> BK2CMP4P_R {
125        BK2CMP4P_R::new(((self.bits >> 13) & 1) != 0)
126    }
127    ///Bits 16:18 - OCREF_CLR source selection
128    #[inline(always)]
129    pub fn ocrsel(&self) -> OCRSEL_R {
130        OCRSEL_R::new(((self.bits >> 16) & 7) as u8)
131    }
132}
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("AF2")
136            .field("ocrsel", &self.ocrsel())
137            .field("bk2cmp4p", &self.bk2cmp4p())
138            .field("bk2cmp3p", &self.bk2cmp3p())
139            .field("bk2cmp2p", &self.bk2cmp2p())
140            .field("bk2cmp1p", &self.bk2cmp1p())
141            .field("bk2inp", &self.bk2inp())
142            .field("bk2cmp7e", &self.bk2cmp7e())
143            .field("bk2cmp6e", &self.bk2cmp6e())
144            .field("bk2cmp5e", &self.bk2cmp5e())
145            .field("bk2cmp4e", &self.bk2cmp4e())
146            .field("bk2cmp3e", &self.bk2cmp3e())
147            .field("bk2cmp2e", &self.bk2cmp2e())
148            .field("bk2cmp1e", &self.bk2cmp1e())
149            .field("bkine", &self.bkine())
150            .finish()
151    }
152}
153impl W {
154    ///Bit 0 - BRK BKIN input enable
155    #[inline(always)]
156    pub fn bkine(&mut self) -> BKINE_W<AF2rs> {
157        BKINE_W::new(self, 0)
158    }
159    ///Bit 1 - BRK2 COMP1 enable
160    #[inline(always)]
161    pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<AF2rs> {
162        BK2CMP1E_W::new(self, 1)
163    }
164    ///Bit 2 - BRK2 COMP2 enable
165    #[inline(always)]
166    pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<AF2rs> {
167        BK2CMP2E_W::new(self, 2)
168    }
169    ///Bit 3 - BRK2 COMP3 enable
170    #[inline(always)]
171    pub fn bk2cmp3e(&mut self) -> BK2CMP3E_W<AF2rs> {
172        BK2CMP3E_W::new(self, 3)
173    }
174    ///Bit 4 - BRK2 COMP4 enable
175    #[inline(always)]
176    pub fn bk2cmp4e(&mut self) -> BK2CMP4E_W<AF2rs> {
177        BK2CMP4E_W::new(self, 4)
178    }
179    ///Bit 5 - BRK2 COMP5 enable
180    #[inline(always)]
181    pub fn bk2cmp5e(&mut self) -> BK2CMP5E_W<AF2rs> {
182        BK2CMP5E_W::new(self, 5)
183    }
184    ///Bit 6 - BRK2 COMP6 enable
185    #[inline(always)]
186    pub fn bk2cmp6e(&mut self) -> BK2CMP6E_W<AF2rs> {
187        BK2CMP6E_W::new(self, 6)
188    }
189    ///Bit 7 - BRK2 COMP7 enable
190    #[inline(always)]
191    pub fn bk2cmp7e(&mut self) -> BK2CMP7E_W<AF2rs> {
192        BK2CMP7E_W::new(self, 7)
193    }
194    ///Bit 9 - BRK2 BKIN input polarity
195    #[inline(always)]
196    pub fn bk2inp(&mut self) -> BK2INP_W<AF2rs> {
197        BK2INP_W::new(self, 9)
198    }
199    ///Bit 10 - BRK2 COMP1 input polarity
200    #[inline(always)]
201    pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<AF2rs> {
202        BK2CMP1P_W::new(self, 10)
203    }
204    ///Bit 11 - BRK2 COMP2 input polarity
205    #[inline(always)]
206    pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<AF2rs> {
207        BK2CMP2P_W::new(self, 11)
208    }
209    ///Bit 12 - BRK2 COMP3 input polarity
210    #[inline(always)]
211    pub fn bk2cmp3p(&mut self) -> BK2CMP3P_W<AF2rs> {
212        BK2CMP3P_W::new(self, 12)
213    }
214    ///Bit 13 - BRK2 COMP4 input polarity
215    #[inline(always)]
216    pub fn bk2cmp4p(&mut self) -> BK2CMP4P_W<AF2rs> {
217        BK2CMP4P_W::new(self, 13)
218    }
219    ///Bits 16:18 - OCREF_CLR source selection
220    #[inline(always)]
221    pub fn ocrsel(&mut self) -> OCRSEL_W<AF2rs> {
222        OCRSEL_W::new(self, 16)
223    }
224}
225/**TIM alternate function option register 2
226
227You can [`read`](crate::Reg::read) this register and get [`af2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
228
229See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:AF2)*/
230pub struct AF2rs;
231impl crate::RegisterSpec for AF2rs {
232    type Ux = u32;
233}
234///`read()` method returns [`af2::R`](R) reader structure
235impl crate::Readable for AF2rs {}
236///`write(|w| ..)` method takes [`af2::W`](W) writer structure
237impl crate::Writable for AF2rs {
238    type Safety = crate::Unsafe;
239}
240///`reset()` method sets AF2 to value 0
241impl crate::Resettable for AF2rs {}
stm32g4/stm32g484/tim1/af2.rs

stm32g4/stm32g484/tim1/
af2.rs
