stm32g4/stm32g484/
tim1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 4],
19    bdtr: BDTR,
20    ccr5: CCR5,
21    ccr6: CCR6,
22    ccmr3_output: CCMR3_OUTPUT,
23    dtr2: DTR2,
24    ecr: ECR,
25    tisel: TISEL,
26    af1: AF1,
27    af2: AF2,
28    _reserved23: [u8; 0x0374],
29    dcr: DCR,
30    dmar: DMAR,
31}
32impl RegisterBlock {
33    ///0x00 - control register 1
34    #[inline(always)]
35    pub const fn cr1(&self) -> &CR1 {
36        &self.cr1
37    }
38    ///0x04 - control register 2
39    #[inline(always)]
40    pub const fn cr2(&self) -> &CR2 {
41        &self.cr2
42    }
43    ///0x08 - slave mode control register
44    #[inline(always)]
45    pub const fn smcr(&self) -> &SMCR {
46        &self.smcr
47    }
48    ///0x0c - DMA/Interrupt enable register
49    #[inline(always)]
50    pub const fn dier(&self) -> &DIER {
51        &self.dier
52    }
53    ///0x10 - status register
54    #[inline(always)]
55    pub const fn sr(&self) -> &SR {
56        &self.sr
57    }
58    ///0x14 - event generation register
59    #[inline(always)]
60    pub const fn egr(&self) -> &EGR {
61        &self.egr
62    }
63    ///0x18 - capture/compare mode register 1 (input mode)
64    #[inline(always)]
65    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
66        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
67    }
68    ///0x18 - capture/compare mode register 1 (output mode)
69    #[inline(always)]
70    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
71        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
72    }
73    ///0x1c - capture/compare mode register 2 (input mode)
74    #[inline(always)]
75    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
76        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
77    }
78    ///0x1c - capture/compare mode register 2 (output mode)
79    #[inline(always)]
80    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
81        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
82    }
83    ///0x20 - capture/compare enable register
84    #[inline(always)]
85    pub const fn ccer(&self) -> &CCER {
86        &self.ccer
87    }
88    ///0x24 - counter
89    #[inline(always)]
90    pub const fn cnt(&self) -> &CNT {
91        &self.cnt
92    }
93    ///0x28 - prescaler
94    #[inline(always)]
95    pub const fn psc(&self) -> &PSC {
96        &self.psc
97    }
98    ///0x2c - auto-reload register
99    #[inline(always)]
100    pub const fn arr(&self) -> &ARR {
101        &self.arr
102    }
103    ///0x30 - repetition counter register
104    #[inline(always)]
105    pub const fn rcr(&self) -> &RCR {
106        &self.rcr
107    }
108    ///0x34..0x44 - capture/compare register
109    ///
110    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
111    #[inline(always)]
112    pub const fn ccr(&self, n: usize) -> &CCR {
113        &self.ccr[n]
114    }
115    ///Iterator for array of:
116    ///0x34..0x44 - capture/compare register
117    #[inline(always)]
118    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
119        self.ccr.iter()
120    }
121    ///0x34 - capture/compare register
122    #[inline(always)]
123    pub const fn ccr1(&self) -> &CCR {
124        self.ccr(0)
125    }
126    ///0x38 - capture/compare register
127    #[inline(always)]
128    pub const fn ccr2(&self) -> &CCR {
129        self.ccr(1)
130    }
131    ///0x3c - capture/compare register
132    #[inline(always)]
133    pub const fn ccr3(&self) -> &CCR {
134        self.ccr(2)
135    }
136    ///0x40 - capture/compare register
137    #[inline(always)]
138    pub const fn ccr4(&self) -> &CCR {
139        self.ccr(3)
140    }
141    ///0x44 - break and dead-time register
142    #[inline(always)]
143    pub const fn bdtr(&self) -> &BDTR {
144        &self.bdtr
145    }
146    ///0x48 - capture/compare register
147    #[inline(always)]
148    pub const fn ccr5(&self) -> &CCR5 {
149        &self.ccr5
150    }
151    ///0x4c - capture/compare register
152    #[inline(always)]
153    pub const fn ccr6(&self) -> &CCR6 {
154        &self.ccr6
155    }
156    ///0x50 - capture/compare mode register 2 (output mode)
157    #[inline(always)]
158    pub const fn ccmr3_output(&self) -> &CCMR3_OUTPUT {
159        &self.ccmr3_output
160    }
161    ///0x54 - timer Deadtime Register 2
162    #[inline(always)]
163    pub const fn dtr2(&self) -> &DTR2 {
164        &self.dtr2
165    }
166    ///0x58 - DMA control register
167    #[inline(always)]
168    pub const fn ecr(&self) -> &ECR {
169        &self.ecr
170    }
171    ///0x5c - TIM timer input selection register
172    #[inline(always)]
173    pub const fn tisel(&self) -> &TISEL {
174        &self.tisel
175    }
176    ///0x60 - TIM alternate function option register 1
177    #[inline(always)]
178    pub const fn af1(&self) -> &AF1 {
179        &self.af1
180    }
181    ///0x64 - TIM alternate function option register 2
182    #[inline(always)]
183    pub const fn af2(&self) -> &AF2 {
184        &self.af2
185    }
186    ///0x3dc - control register
187    #[inline(always)]
188    pub const fn dcr(&self) -> &DCR {
189        &self.dcr
190    }
191    ///0x3e0 - DMA address for full transfer
192    #[inline(always)]
193    pub const fn dmar(&self) -> &DMAR {
194        &self.dmar
195    }
196}
197/**CR1 (rw) register accessor: control register 1
198
199You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CR1)
202
203For information about available fields see [`mod@cr1`] module*/
204pub type CR1 = crate::Reg<cr1::CR1rs>;
205///control register 1
206pub mod cr1;
207/**CR2 (rw) register accessor: control register 2
208
209You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CR2)
212
213For information about available fields see [`mod@cr2`] module*/
214pub type CR2 = crate::Reg<cr2::CR2rs>;
215///control register 2
216pub mod cr2;
217/**SMCR (rw) register accessor: slave mode control register
218
219You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:SMCR)
222
223For information about available fields see [`mod@smcr`] module*/
224pub type SMCR = crate::Reg<smcr::SMCRrs>;
225///slave mode control register
226pub mod smcr;
227/**DIER (rw) register accessor: DMA/Interrupt enable register
228
229You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
230
231See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:DIER)
232
233For information about available fields see [`mod@dier`] module*/
234pub type DIER = crate::Reg<dier::DIERrs>;
235///DMA/Interrupt enable register
236pub mod dier;
237/**SR (rw) register accessor: status register
238
239You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
240
241See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:SR)
242
243For information about available fields see [`mod@sr`] module*/
244pub type SR = crate::Reg<sr::SRrs>;
245///status register
246pub mod sr;
247/**EGR (w) register accessor: event generation register
248
249You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:EGR)
252
253For information about available fields see [`mod@egr`] module*/
254pub type EGR = crate::Reg<egr::EGRrs>;
255///event generation register
256pub mod egr;
257/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
258
259You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
260
261See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCMR1_Output)
262
263For information about available fields see [`mod@ccmr1_output`] module*/
264#[doc(alias = "CCMR1_Output")]
265pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
266///capture/compare mode register 1 (output mode)
267pub mod ccmr1_output;
268/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
269
270You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCMR1_Input)
273
274For information about available fields see [`mod@ccmr1_input`] module*/
275#[doc(alias = "CCMR1_Input")]
276pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
277///capture/compare mode register 1 (input mode)
278pub mod ccmr1_input;
279/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
280
281You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
282
283See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCMR2_Output)
284
285For information about available fields see [`mod@ccmr2_output`] module*/
286#[doc(alias = "CCMR2_Output")]
287pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
288///capture/compare mode register 2 (output mode)
289pub mod ccmr2_output;
290/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
291
292You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCMR2_Input)
295
296For information about available fields see [`mod@ccmr2_input`] module*/
297#[doc(alias = "CCMR2_Input")]
298pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
299///capture/compare mode register 2 (input mode)
300pub mod ccmr2_input;
301/**CCER (rw) register accessor: capture/compare enable register
302
303You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
304
305See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCER)
306
307For information about available fields see [`mod@ccer`] module*/
308pub type CCER = crate::Reg<ccer::CCERrs>;
309///capture/compare enable register
310pub mod ccer;
311/**CNT (rw) register accessor: counter
312
313You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
314
315See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CNT)
316
317For information about available fields see [`mod@cnt`] module*/
318pub type CNT = crate::Reg<cnt::CNTrs>;
319///counter
320pub mod cnt;
321/**PSC (rw) register accessor: prescaler
322
323You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
324
325See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:PSC)
326
327For information about available fields see [`mod@psc`] module*/
328pub type PSC = crate::Reg<psc::PSCrs>;
329///prescaler
330pub mod psc;
331/**ARR (rw) register accessor: auto-reload register
332
333You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
334
335See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:ARR)
336
337For information about available fields see [`mod@arr`] module*/
338pub type ARR = crate::Reg<arr::ARRrs>;
339///auto-reload register
340pub mod arr;
341/**RCR (rw) register accessor: repetition counter register
342
343You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
344
345See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:RCR)
346
347For information about available fields see [`mod@rcr`] module*/
348pub type RCR = crate::Reg<rcr::RCRrs>;
349///repetition counter register
350pub mod rcr;
351/**CCR (rw) register accessor: capture/compare register
352
353You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
354
355See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCR[1])
356
357For information about available fields see [`mod@ccr`] module*/
358pub type CCR = crate::Reg<ccr::CCRrs>;
359///capture/compare register
360pub mod ccr;
361/**BDTR (rw) register accessor: break and dead-time register
362
363You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
364
365See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:BDTR)
366
367For information about available fields see [`mod@bdtr`] module*/
368pub type BDTR = crate::Reg<bdtr::BDTRrs>;
369///break and dead-time register
370pub mod bdtr;
371/**CCR5 (rw) register accessor: capture/compare register
372
373You can [`read`](crate::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
374
375See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCR5)
376
377For information about available fields see [`mod@ccr5`] module*/
378pub type CCR5 = crate::Reg<ccr5::CCR5rs>;
379///capture/compare register
380pub mod ccr5;
381pub use ccr as ccr6;
382pub use CCR as CCR6;
383/**CCMR3_Output (rw) register accessor: capture/compare mode register 2 (output mode)
384
385You can [`read`](crate::Reg::read) this register and get [`ccmr3_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr3_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
386
387See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:CCMR3_Output)
388
389For information about available fields see [`mod@ccmr3_output`] module*/
390#[doc(alias = "CCMR3_Output")]
391pub type CCMR3_OUTPUT = crate::Reg<ccmr3_output::CCMR3_OUTPUTrs>;
392///capture/compare mode register 2 (output mode)
393pub mod ccmr3_output;
394/**DTR2 (rw) register accessor: timer Deadtime Register 2
395
396You can [`read`](crate::Reg::read) this register and get [`dtr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
397
398See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:DTR2)
399
400For information about available fields see [`mod@dtr2`] module*/
401pub type DTR2 = crate::Reg<dtr2::DTR2rs>;
402///timer Deadtime Register 2
403pub mod dtr2;
404/**ECR (rw) register accessor: DMA control register
405
406You can [`read`](crate::Reg::read) this register and get [`ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
407
408See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:ECR)
409
410For information about available fields see [`mod@ecr`] module*/
411pub type ECR = crate::Reg<ecr::ECRrs>;
412///DMA control register
413pub mod ecr;
414/**TISEL (rw) register accessor: TIM timer input selection register
415
416You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
417
418See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:TISEL)
419
420For information about available fields see [`mod@tisel`] module*/
421pub type TISEL = crate::Reg<tisel::TISELrs>;
422///TIM timer input selection register
423pub mod tisel;
424/**AF1 (rw) register accessor: TIM alternate function option register 1
425
426You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
427
428See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:AF1)
429
430For information about available fields see [`mod@af1`] module*/
431pub type AF1 = crate::Reg<af1::AF1rs>;
432///TIM alternate function option register 1
433pub mod af1;
434/**AF2 (rw) register accessor: TIM alternate function option register 2
435
436You can [`read`](crate::Reg::read) this register and get [`af2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
437
438See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:AF2)
439
440For information about available fields see [`mod@af2`] module*/
441pub type AF2 = crate::Reg<af2::AF2rs>;
442///TIM alternate function option register 2
443pub mod af2;
444/**DCR (rw) register accessor: control register
445
446You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
447
448See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:DCR)
449
450For information about available fields see [`mod@dcr`] module*/
451pub type DCR = crate::Reg<dcr::DCRrs>;
452///control register
453pub mod dcr;
454/**DMAR (rw) register accessor: DMA address for full transfer
455
456You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
457
458See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1:DMAR)
459
460For information about available fields see [`mod@dmar`] module*/
461pub type DMAR = crate::Reg<dmar::DMARrs>;
462///DMA address for full transfer
463pub mod dmar;
stm32g4/stm32g484/tim1.rs

stm32g4/stm32g484/
tim1.rs
