Type Definition stm32g4::stm32g484::hrtim_master::mcr::R[][src]

type R = R<u32, MCR>;

Reader of register MCR

Implementations

impl R[src]

pub fn brstdma(&self) -> BRSTDMA_R[src]

Bits 30:31 - Burst DMA Update

pub fn mrepu(&self) -> MREPU_R[src]

Bit 29 - Master Timer Repetition update

pub fn preen(&self) -> PREEN_R[src]

Bit 27 - Preload enable

pub fn dacsync(&self) -> DACSYNC_R[src]

Bits 25:26 - AC Synchronization

pub fn tfcen(&self) -> TFCEN_R[src]

Bit 22 - Timer F counter enable

pub fn tecen(&self) -> TECEN_R[src]

Bit 21 - Timer E counter enable

pub fn tdcen(&self) -> TDCEN_R[src]

Bit 20 - Timer D counter enable

pub fn tccen(&self) -> TCCEN_R[src]

Bit 19 - Timer C counter enable

pub fn tbcen(&self) -> TBCEN_R[src]

Bit 18 - Timer B counter enable

pub fn tacen(&self) -> TACEN_R[src]

Bit 17 - Timer A counter enable

pub fn mcen(&self) -> MCEN_R[src]

Bit 16 - Master Counter enable

pub fn sync_src(&self) -> SYNC_SRC_R[src]

Bits 14:15 - Synchronization source

pub fn sync_out(&self) -> SYNC_OUT_R[src]

Bits 12:13 - Synchronization output

pub fn syncstrtm(&self) -> SYNCSTRTM_R[src]

Bit 11 - Synchronization Starts Master

pub fn syncrstm(&self) -> SYNCRSTM_R[src]

Bit 10 - Synchronization Resets Master

pub fn sync_in(&self) -> SYNC_IN_R[src]

Bits 8:9 - synchronization input

pub fn intlvd(&self) -> INTLVD_R[src]

Bits 6:7 - Interleaved mode

pub fn half(&self) -> HALF_R[src]

Bit 5 - Half mode enable

pub fn retrig(&self) -> RETRIG_R[src]

Bit 4 - Master Re-triggerable mode

pub fn cont(&self) -> CONT_R[src]

Bit 3 - Master Continuous mode

pub fn ck_psc(&self) -> CK_PSC_R[src]

Bits 0:2 - HRTIM Master Clock prescaler