Type Definition stm32g4::stm32g474::rcc::pllcfgr::W

type W = W<u32, PLLCFGR>;

Writer for register PLLCFGR

Implementations

impl W

pub fn pllpdiv(&mut self) -> PLLPDIV_W<'_>

Bits 27:31 - Main PLL division factor for PLLSAI2CLK

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:7 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source