Struct stm32g4::stm32g431::dma1::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub isr: ISR,
    pub ifcr: IFCR,
    pub ccr1: CCR1,
    pub cndtr1: CNDTR1,
    pub cpar1: CPAR1,
    pub cmar1: CMAR1,
    pub ccr2: CCR2,
    pub cndtr2: CNDTR2,
    pub cpar2: CPAR2,
    pub cmar2: CMAR2,
    pub ccr3: CCR3,
    pub cndtr3: CNDTR3,
    pub cpar3: CPAR3,
    pub cmar3: CMAR3,
    pub ccr4: CCR4,
    pub cndtr4: CNDTR4,
    pub cpar4: CPAR4,
    pub cmar4: CMAR4,
    pub ccr5: CCR5,
    pub cndtr5: CNDTR5,
    pub cpar5: CPAR5,
    pub cmar5: CMAR5,
    pub ccr6: CCR6,
    pub cndtr6: CNDTR6,
    pub cpar6: CPAR6,
    pub cmar6: CMAR6,
    pub ccr7: CCR7,
    pub cndtr7: CNDTR7,
    pub cpar7: CPAR7,
    pub cmar7: CMAR7,
    pub ccr8: CCR8,
    pub cndtr8: CNDTR8,
    pub cpar8: CPAR8,
    pub cmar8: CMAR8,
    // some fields omitted
}

Register block

Fields

isr: ISR

0x00 - interrupt status register

ifcr: IFCR

0x04 - DMA interrupt flag clear register

ccr1: CCR1

0x08 - DMA channel 1 configuration register

cndtr1: CNDTR1

0x0c - channel x number of data to transfer register

cpar1: CPAR1

0x10 - DMA channel x peripheral address register

cmar1: CMAR1

0x14 - DMA channel x memory address register

ccr2: CCR2

0x1c - DMA channel 2 configuration register

cndtr2: CNDTR2

0x20 - channel x number of data to transfer register

cpar2: CPAR2

0x24 - DMA channel x peripheral address register

cmar2: CMAR2

0x28 - DMA channel x memory address register

ccr3: CCR3

0x30 - DMA channel 3 configuration register

cndtr3: CNDTR3

0x34 - channel x number of data to transfer register

cpar3: CPAR3

0x38 - DMA channel x peripheral address register

cmar3: CMAR3

0x3c - DMA channel x memory address register

ccr4: CCR4

0x44 - DMA channel 3 configuration register

cndtr4: CNDTR4

0x48 - channel x number of data to transfer register

cpar4: CPAR4

0x4c - DMA channel x peripheral address register

cmar4: CMAR4

0x50 - DMA channel x memory address register

ccr5: CCR5

0x58 - DMA channel 4 configuration register

cndtr5: CNDTR5

0x5c - channel x number of data to transfer register

cpar5: CPAR5

0x60 - DMA channel x peripheral address register

cmar5: CMAR5

0x64 - DMA channel x memory address register

ccr6: CCR6

0x6c - DMA channel 5 configuration register

cndtr6: CNDTR6

0x70 - channel x number of data to transfer register

cpar6: CPAR6

0x74 - DMA channel x peripheral address register

cmar6: CMAR6

0x78 - DMA channel x memory address register

ccr7: CCR7

0x80 - DMA channel 6 configuration register

cndtr7: CNDTR7

0x84 - channel x number of data to transfer register

cpar7: CPAR7

0x88 - DMA channel x peripheral address register

cmar7: CMAR7

0x8c - DMA channel x memory address register

ccr8: CCR8

0x94 - DMA channel 7 configuration register

cndtr8: CNDTR8

0x98 - channel x number of data to transfer register

cpar8: CPAR8

0x9c - DMA channel x peripheral address register

cmar8: CMAR8

0xa0 - DMA channel x memory address register

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    U: From<T>, [src]

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    U: TryFrom<T>, [src]

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