Type Definition stm32g4::stm32g431::dac1::dac_sr::R

type R = R<u32, DAC_SR>;

Reader of register DAC_SR

Implementations

impl R

pub fn dac1rdy(&self) -> DAC1RDY_R

Bit 11 - DAC channel1 ready status bit

pub fn dorstat1(&self) -> DORSTAT1_R

Bit 12 - DAC channel1 output register status bit

pub fn dmaudr1(&self) -> DMAUDR1_R

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag1(&self) -> CAL_FLAG1_R

Bit 14 - DAC Channel 1 calibration offset status This bit is set and cleared by hardware

pub fn bwst1(&self) -> BWST1_R

Bit 15 - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).

pub fn dac2rdy(&self) -> DAC2RDY_R

Bit 27 - DAC channel 2 ready status bit

pub fn dorstat2(&self) -> DORSTAT2_R

Bit 28 - DAC channel 2 output register status bit

pub fn dmaudr2(&self) -> DMAUDR2_R

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag2(&self) -> CAL_FLAG2_R

Bit 30 - DAC Channel 2 calibration offset status This bit is set and cleared by hardware

pub fn bwst2(&self) -> BWST2_R

Bit 31 - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).