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#[doc = "Reader of register ISR"] pub type R = crate::R<u32, super::ISR>; #[doc = "Writer for register ISR"] pub type W = crate::W<u32, super::ISR>; #[doc = "Register ISR `reset()`'s with value 0x01"] impl crate::ResetValue for super::ISR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x01 } } #[doc = "Reader of field `ADDCODE`"] pub type ADDCODE_R = crate::R<u8, u8>; #[doc = "Reader of field `DIR`"] pub type DIR_R = crate::R<bool, bool>; #[doc = "Reader of field `BUSY`"] pub type BUSY_R = crate::R<bool, bool>; #[doc = "Reader of field `ALERT`"] pub type ALERT_R = crate::R<bool, bool>; #[doc = "Reader of field `TIMEOUT`"] pub type TIMEOUT_R = crate::R<bool, bool>; #[doc = "Reader of field `PECERR`"] pub type PECERR_R = crate::R<bool, bool>; #[doc = "Reader of field `OVR`"] pub type OVR_R = crate::R<bool, bool>; #[doc = "Reader of field `ARLO`"] pub type ARLO_R = crate::R<bool, bool>; #[doc = "Reader of field `BERR`"] pub type BERR_R = crate::R<bool, bool>; #[doc = "Reader of field `TCR`"] pub type TCR_R = crate::R<bool, bool>; #[doc = "Reader of field `TC`"] pub type TC_R = crate::R<bool, bool>; #[doc = "Reader of field `STOPF`"] pub type STOPF_R = crate::R<bool, bool>; #[doc = "Reader of field `NACKF`"] pub type NACKF_R = crate::R<bool, bool>; #[doc = "Reader of field `ADDR`"] pub type ADDR_R = crate::R<bool, bool>; #[doc = "Reader of field `RXNE`"] pub type RXNE_R = crate::R<bool, bool>; #[doc = "Reader of field `TXIS`"] pub type TXIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TXIS`"] pub struct TXIS_W<'a> { w: &'a mut W, } impl<'a> TXIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `TXE`"] pub type TXE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TXE`"] pub struct TXE_W<'a> { w: &'a mut W, } impl<'a> TXE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bits 17:23 - Address match code (Slave mode)"] #[inline(always)] pub fn addcode(&self) -> ADDCODE_R { ADDCODE_R::new(((self.bits >> 17) & 0x7f) as u8) } #[doc = "Bit 16 - Transfer direction (Slave mode)"] #[inline(always)] pub fn dir(&self) -> DIR_R { DIR_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 15 - Bus busy"] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 13 - SMBus alert"] #[inline(always)] pub fn alert(&self) -> ALERT_R { ALERT_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 12 - Timeout or t_low detection flag"] #[inline(always)] pub fn timeout(&self) -> TIMEOUT_R { TIMEOUT_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 11 - PEC Error in reception"] #[inline(always)] pub fn pecerr(&self) -> PECERR_R { PECERR_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 10 - Overrun/Underrun (slave mode)"] #[inline(always)] pub fn ovr(&self) -> OVR_R { OVR_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 9 - Arbitration lost"] #[inline(always)] pub fn arlo(&self) -> ARLO_R { ARLO_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bit 8 - Bus error"] #[inline(always)] pub fn berr(&self) -> BERR_R { BERR_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 7 - Transfer Complete Reload"] #[inline(always)] pub fn tcr(&self) -> TCR_R { TCR_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 6 - Transfer Complete (master mode)"] #[inline(always)] pub fn tc(&self) -> TC_R { TC_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 5 - Stop detection flag"] #[inline(always)] pub fn stopf(&self) -> STOPF_R { STOPF_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 4 - Not acknowledge received flag"] #[inline(always)] pub fn nackf(&self) -> NACKF_R { NACKF_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 3 - Address matched (slave mode)"] #[inline(always)] pub fn addr(&self) -> ADDR_R { ADDR_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 2 - Receive data register not empty (receivers)"] #[inline(always)] pub fn rxne(&self) -> RXNE_R { RXNE_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 1 - Transmit interrupt status (transmitters)"] #[inline(always)] pub fn txis(&self) -> TXIS_R { TXIS_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - Transmit data register empty (transmitters)"] #[inline(always)] pub fn txe(&self) -> TXE_R { TXE_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bit 1 - Transmit interrupt status (transmitters)"] #[inline(always)] pub fn txis(&mut self) -> TXIS_W { TXIS_W { w: self } } #[doc = "Bit 0 - Transmit data register empty (transmitters)"] #[inline(always)] pub fn txe(&mut self) -> TXE_W { TXE_W { w: self } } }