1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
#[doc = "Reader of register SR"] pub type R = crate::R<u32, super::SR>; #[doc = "Writer for register SR"] pub type W = crate::W<u32, super::SR>; #[doc = "Register SR `reset()`'s with value 0"] impl crate::ResetValue for super::SR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SEIS`"] pub type SEIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SEIS`"] pub struct SEIS_W<'a> { w: &'a mut W, } impl<'a> SEIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Reader of field `CEIS`"] pub type CEIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CEIS`"] pub struct CEIS_W<'a> { w: &'a mut W, } impl<'a> CEIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "Reader of field `SECS`"] pub type SECS_R = crate::R<bool, bool>; #[doc = "Reader of field `CECS`"] pub type CECS_R = crate::R<bool, bool>; #[doc = "Reader of field `DRDY`"] pub type DRDY_R = crate::R<bool, bool>; impl R { #[doc = "Bit 6 - Seed error interrupt status"] #[inline(always)] pub fn seis(&self) -> SEIS_R { SEIS_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 5 - Clock error interrupt status"] #[inline(always)] pub fn ceis(&self) -> CEIS_R { CEIS_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 2 - Seed error current status"] #[inline(always)] pub fn secs(&self) -> SECS_R { SECS_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 1 - Clock error current status"] #[inline(always)] pub fn cecs(&self) -> CECS_R { CECS_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - Data ready"] #[inline(always)] pub fn drdy(&self) -> DRDY_R { DRDY_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bit 6 - Seed error interrupt status"] #[inline(always)] pub fn seis(&mut self) -> SEIS_W { SEIS_W { w: self } } #[doc = "Bit 5 - Clock error interrupt status"] #[inline(always)] pub fn ceis(&mut self) -> CEIS_W { CEIS_W { w: self } } }