1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248
#[doc = "Reader of register DAC_SR"] pub type R = crate::R<u32, super::DAC_SR>; #[doc = "Writer for register DAC_SR"] pub type W = crate::W<u32, super::DAC_SR>; #[doc = "Register DAC_SR `reset()`'s with value 0"] impl crate::ResetValue for super::DAC_SR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `DAC1RDY`"] pub type DAC1RDY_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DAC1RDY`"] pub struct DAC1RDY_W<'a> { w: &'a mut W, } impl<'a> DAC1RDY_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `DORSTAT1`"] pub type DORSTAT1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DORSTAT1`"] pub struct DORSTAT1_W<'a> { w: &'a mut W, } impl<'a> DORSTAT1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `DMAUDR1`"] pub type DMAUDR1_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAUDR1`"] pub struct DMAUDR1_W<'a> { w: &'a mut W, } impl<'a> DMAUDR1_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `CAL_FLAG1`"] pub type CAL_FLAG1_R = crate::R<bool, bool>; #[doc = "Reader of field `BWST1`"] pub type BWST1_R = crate::R<bool, bool>; #[doc = "Reader of field `DAC2RDY`"] pub type DAC2RDY_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DAC2RDY`"] pub struct DAC2RDY_W<'a> { w: &'a mut W, } impl<'a> DAC2RDY_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27); self.w } } #[doc = "Reader of field `DORSTAT2`"] pub type DORSTAT2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DORSTAT2`"] pub struct DORSTAT2_W<'a> { w: &'a mut W, } impl<'a> DORSTAT2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Reader of field `DMAUDR2`"] pub type DMAUDR2_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMAUDR2`"] pub struct DMAUDR2_W<'a> { w: &'a mut W, } impl<'a> DMAUDR2_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Reader of field `CAL_FLAG2`"] pub type CAL_FLAG2_R = crate::R<bool, bool>; #[doc = "Reader of field `BWST2`"] pub type BWST2_R = crate::R<bool, bool>; impl R { #[doc = "Bit 11 - DAC channel1 ready status bit"] #[inline(always)] pub fn dac1rdy(&self) -> DAC1RDY_R { DAC1RDY_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 12 - DAC channel1 output register status bit"] #[inline(always)] pub fn dorstat1(&self) -> DORSTAT1_R { DORSTAT1_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)."] #[inline(always)] pub fn dmaudr1(&self) -> DMAUDR1_R { DMAUDR1_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 14 - DAC Channel 1 calibration offset status This bit is set and cleared by hardware"] #[inline(always)] pub fn cal_flag1(&self) -> CAL_FLAG1_R { CAL_FLAG1_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 15 - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization)."] #[inline(always)] pub fn bwst1(&self) -> BWST1_R { BWST1_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 27 - DAC channel 2 ready status bit"] #[inline(always)] pub fn dac2rdy(&self) -> DAC2RDY_R { DAC2RDY_R::new(((self.bits >> 27) & 0x01) != 0) } #[doc = "Bit 28 - DAC channel 2 output register status bit"] #[inline(always)] pub fn dorstat2(&self) -> DORSTAT2_R { DORSTAT2_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)."] #[inline(always)] pub fn dmaudr2(&self) -> DMAUDR2_R { DMAUDR2_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 30 - DAC Channel 2 calibration offset status This bit is set and cleared by hardware"] #[inline(always)] pub fn cal_flag2(&self) -> CAL_FLAG2_R { CAL_FLAG2_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization)."] #[inline(always)] pub fn bwst2(&self) -> BWST2_R { BWST2_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bit 11 - DAC channel1 ready status bit"] #[inline(always)] pub fn dac1rdy(&mut self) -> DAC1RDY_W { DAC1RDY_W { w: self } } #[doc = "Bit 12 - DAC channel1 output register status bit"] #[inline(always)] pub fn dorstat1(&mut self) -> DORSTAT1_W { DORSTAT1_W { w: self } } #[doc = "Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)."] #[inline(always)] pub fn dmaudr1(&mut self) -> DMAUDR1_W { DMAUDR1_W { w: self } } #[doc = "Bit 27 - DAC channel 2 ready status bit"] #[inline(always)] pub fn dac2rdy(&mut self) -> DAC2RDY_W { DAC2RDY_W { w: self } } #[doc = "Bit 28 - DAC channel 2 output register status bit"] #[inline(always)] pub fn dorstat2(&mut self) -> DORSTAT2_W { DORSTAT2_W { w: self } } #[doc = "Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)."] #[inline(always)] pub fn dmaudr2(&mut self) -> DMAUDR2_W { DMAUDR2_W { w: self } } }