1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
#[doc = "Reader of register SR"] pub type R = crate::R<u32, super::SR>; #[doc = "Writer for register SR"] pub type W = crate::W<u32, super::SR>; #[doc = "Register SR `reset()`'s with value 0x02"] impl crate::ResetValue for super::SR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x02 } } #[doc = "Reader of field `RXNE`"] pub type RXNE_R = crate::R<bool, bool>; #[doc = "Reader of field `TXE`"] pub type TXE_R = crate::R<bool, bool>; #[doc = "Reader of field `CRCERR`"] pub type CRCERR_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CRCERR`"] pub struct CRCERR_W<'a> { w: &'a mut W, } impl<'a> CRCERR_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `MODF`"] pub type MODF_R = crate::R<bool, bool>; #[doc = "Reader of field `OVR`"] pub type OVR_R = crate::R<bool, bool>; #[doc = "Reader of field `BSY`"] pub type BSY_R = crate::R<bool, bool>; #[doc = "Reader of field `TIFRFE`"] pub type TIFRFE_R = crate::R<bool, bool>; #[doc = "Reader of field `FRLVL`"] pub type FRLVL_R = crate::R<u8, u8>; #[doc = "Reader of field `FTLVL`"] pub type FTLVL_R = crate::R<u8, u8>; impl R { #[doc = "Bit 0 - Receive buffer not empty"] #[inline(always)] pub fn rxne(&self) -> RXNE_R { RXNE_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - Transmit buffer empty"] #[inline(always)] pub fn txe(&self) -> TXE_R { TXE_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 4 - CRC error flag"] #[inline(always)] pub fn crcerr(&self) -> CRCERR_R { CRCERR_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 5 - Mode fault"] #[inline(always)] pub fn modf(&self) -> MODF_R { MODF_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Overrun flag"] #[inline(always)] pub fn ovr(&self) -> OVR_R { OVR_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Busy flag"] #[inline(always)] pub fn bsy(&self) -> BSY_R { BSY_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - TI frame format error"] #[inline(always)] pub fn tifrfe(&self) -> TIFRFE_R { TIFRFE_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bits 9:10 - FIFO reception level"] #[inline(always)] pub fn frlvl(&self) -> FRLVL_R { FRLVL_R::new(((self.bits >> 9) & 0x03) as u8) } #[doc = "Bits 11:12 - FIFO transmission level"] #[inline(always)] pub fn ftlvl(&self) -> FTLVL_R { FTLVL_R::new(((self.bits >> 11) & 0x03) as u8) } } impl W { #[doc = "Bit 4 - CRC error flag"] #[inline(always)] pub fn crcerr(&mut self) -> CRCERR_W { CRCERR_W { w: self } } }