stm32g4_staging/stm32g474/hrtim_time/
set1r.rs

1///Register `SET1R` reader
2pub type R = crate::R<SET1Rrs>;
3///Register `SET1R` writer
4pub type W = crate::W<SET1Rrs>;
5/**Software Set trigger
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum SST {
11    ///0: No effect
12    NoEffect = 0,
13    ///1: Force output to its active state
14    SetActive = 1,
15}
16impl From<SST> for bool {
17    #[inline(always)]
18    fn from(variant: SST) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `SST` reader - Software Set trigger
23pub type SST_R = crate::BitReader<SST>;
24impl SST_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> SST {
28        match self.bits {
29            false => SST::NoEffect,
30            true => SST::SetActive,
31        }
32    }
33    ///No effect
34    #[inline(always)]
35    pub fn is_no_effect(&self) -> bool {
36        *self == SST::NoEffect
37    }
38    ///Force output to its active state
39    #[inline(always)]
40    pub fn is_set_active(&self) -> bool {
41        *self == SST::SetActive
42    }
43}
44///Field `SST` writer - Software Set trigger
45pub type SST_W<'a, REG> = crate::BitWriter<'a, REG, SST>;
46impl<'a, REG> SST_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///No effect
51    #[inline(always)]
52    pub fn no_effect(self) -> &'a mut crate::W<REG> {
53        self.variant(SST::NoEffect)
54    }
55    ///Force output to its active state
56    #[inline(always)]
57    pub fn set_active(self) -> &'a mut crate::W<REG> {
58        self.variant(SST::SetActive)
59    }
60}
61/**Timer A resynchronizaton
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RESYNC {
67    ///0: Timer reset event coming solely from software or SYNC input event has no effect
68    NoEffect = 0,
69    ///1: Timer reset event coming solely from software or SYNC input event forces the output to its active state
70    SetActive = 1,
71}
72impl From<RESYNC> for bool {
73    #[inline(always)]
74    fn from(variant: RESYNC) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `RESYNC` reader - Timer A resynchronizaton
79pub type RESYNC_R = crate::BitReader<RESYNC>;
80impl RESYNC_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> RESYNC {
84        match self.bits {
85            false => RESYNC::NoEffect,
86            true => RESYNC::SetActive,
87        }
88    }
89    ///Timer reset event coming solely from software or SYNC input event has no effect
90    #[inline(always)]
91    pub fn is_no_effect(&self) -> bool {
92        *self == RESYNC::NoEffect
93    }
94    ///Timer reset event coming solely from software or SYNC input event forces the output to its active state
95    #[inline(always)]
96    pub fn is_set_active(&self) -> bool {
97        *self == RESYNC::SetActive
98    }
99}
100///Field `RESYNC` writer - Timer A resynchronizaton
101pub type RESYNC_W<'a, REG> = crate::BitWriter<'a, REG, RESYNC>;
102impl<'a, REG> RESYNC_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Timer reset event coming solely from software or SYNC input event has no effect
107    #[inline(always)]
108    pub fn no_effect(self) -> &'a mut crate::W<REG> {
109        self.variant(RESYNC::NoEffect)
110    }
111    ///Timer reset event coming solely from software or SYNC input event forces the output to its active state
112    #[inline(always)]
113    pub fn set_active(self) -> &'a mut crate::W<REG> {
114        self.variant(RESYNC::SetActive)
115    }
116}
117/**Timer A Period
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum PER {
123    ///0: Timer period event has no effect
124    NoEffect = 0,
125    ///1: Timer period event forces the output to its active state
126    SetActive = 1,
127}
128impl From<PER> for bool {
129    #[inline(always)]
130    fn from(variant: PER) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `PER` reader - Timer A Period
135pub type PER_R = crate::BitReader<PER>;
136impl PER_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> PER {
140        match self.bits {
141            false => PER::NoEffect,
142            true => PER::SetActive,
143        }
144    }
145    ///Timer period event has no effect
146    #[inline(always)]
147    pub fn is_no_effect(&self) -> bool {
148        *self == PER::NoEffect
149    }
150    ///Timer period event forces the output to its active state
151    #[inline(always)]
152    pub fn is_set_active(&self) -> bool {
153        *self == PER::SetActive
154    }
155}
156///Field `PER` writer - Timer A Period
157pub type PER_W<'a, REG> = crate::BitWriter<'a, REG, PER>;
158impl<'a, REG> PER_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Timer period event has no effect
163    #[inline(always)]
164    pub fn no_effect(self) -> &'a mut crate::W<REG> {
165        self.variant(PER::NoEffect)
166    }
167    ///Timer period event forces the output to its active state
168    #[inline(always)]
169    pub fn set_active(self) -> &'a mut crate::W<REG> {
170        self.variant(PER::SetActive)
171    }
172}
173/**Timer A compare %s
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum CMP1 {
179    ///0: Timer compare event has no effect
180    NoEffect = 0,
181    ///1: Timer compare event forces the output to its active state
182    SetActive = 1,
183}
184impl From<CMP1> for bool {
185    #[inline(always)]
186    fn from(variant: CMP1) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `CMP(1-4)` reader - Timer A compare %s
191pub type CMP_R = crate::BitReader<CMP1>;
192impl CMP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> CMP1 {
196        match self.bits {
197            false => CMP1::NoEffect,
198            true => CMP1::SetActive,
199        }
200    }
201    ///Timer compare event has no effect
202    #[inline(always)]
203    pub fn is_no_effect(&self) -> bool {
204        *self == CMP1::NoEffect
205    }
206    ///Timer compare event forces the output to its active state
207    #[inline(always)]
208    pub fn is_set_active(&self) -> bool {
209        *self == CMP1::SetActive
210    }
211}
212///Field `CMP(1-4)` writer - Timer A compare %s
213pub type CMP_W<'a, REG> = crate::BitWriter<'a, REG, CMP1>;
214impl<'a, REG> CMP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Timer compare event has no effect
219    #[inline(always)]
220    pub fn no_effect(self) -> &'a mut crate::W<REG> {
221        self.variant(CMP1::NoEffect)
222    }
223    ///Timer compare event forces the output to its active state
224    #[inline(always)]
225    pub fn set_active(self) -> &'a mut crate::W<REG> {
226        self.variant(CMP1::SetActive)
227    }
228}
229/**Master Period
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum MSTPER {
235    ///0: Master timer counter roll-over/reset has no effect
236    NoEffect = 0,
237    ///1: Master timer counter roll-over/reset forces the output to its active state
238    SetActive = 1,
239}
240impl From<MSTPER> for bool {
241    #[inline(always)]
242    fn from(variant: MSTPER) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `MSTPER` reader - Master Period
247pub type MSTPER_R = crate::BitReader<MSTPER>;
248impl MSTPER_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> MSTPER {
252        match self.bits {
253            false => MSTPER::NoEffect,
254            true => MSTPER::SetActive,
255        }
256    }
257    ///Master timer counter roll-over/reset has no effect
258    #[inline(always)]
259    pub fn is_no_effect(&self) -> bool {
260        *self == MSTPER::NoEffect
261    }
262    ///Master timer counter roll-over/reset forces the output to its active state
263    #[inline(always)]
264    pub fn is_set_active(&self) -> bool {
265        *self == MSTPER::SetActive
266    }
267}
268///Field `MSTPER` writer - Master Period
269pub type MSTPER_W<'a, REG> = crate::BitWriter<'a, REG, MSTPER>;
270impl<'a, REG> MSTPER_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///Master timer counter roll-over/reset has no effect
275    #[inline(always)]
276    pub fn no_effect(self) -> &'a mut crate::W<REG> {
277        self.variant(MSTPER::NoEffect)
278    }
279    ///Master timer counter roll-over/reset forces the output to its active state
280    #[inline(always)]
281    pub fn set_active(self) -> &'a mut crate::W<REG> {
282        self.variant(MSTPER::SetActive)
283    }
284}
285/**Master Compare %s
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum MSTCMP1 {
291    ///0: Master timer compare event has no effect
292    NoEffect = 0,
293    ///1: Master timer compare event forces the output to its active state
294    SetActive = 1,
295}
296impl From<MSTCMP1> for bool {
297    #[inline(always)]
298    fn from(variant: MSTCMP1) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `MSTCMP(1-4)` reader - Master Compare %s
303pub type MSTCMP_R = crate::BitReader<MSTCMP1>;
304impl MSTCMP_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> MSTCMP1 {
308        match self.bits {
309            false => MSTCMP1::NoEffect,
310            true => MSTCMP1::SetActive,
311        }
312    }
313    ///Master timer compare event has no effect
314    #[inline(always)]
315    pub fn is_no_effect(&self) -> bool {
316        *self == MSTCMP1::NoEffect
317    }
318    ///Master timer compare event forces the output to its active state
319    #[inline(always)]
320    pub fn is_set_active(&self) -> bool {
321        *self == MSTCMP1::SetActive
322    }
323}
324///Field `MSTCMP(1-4)` writer - Master Compare %s
325pub type MSTCMP_W<'a, REG> = crate::BitWriter<'a, REG, MSTCMP1>;
326impl<'a, REG> MSTCMP_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Master timer compare event has no effect
331    #[inline(always)]
332    pub fn no_effect(self) -> &'a mut crate::W<REG> {
333        self.variant(MSTCMP1::NoEffect)
334    }
335    ///Master timer compare event forces the output to its active state
336    #[inline(always)]
337    pub fn set_active(self) -> &'a mut crate::W<REG> {
338        self.variant(MSTCMP1::SetActive)
339    }
340}
341/**Timer A Compare 4
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum TIMACMP4 {
347    ///0: Timer event has no effect
348    NoEffect = 0,
349    ///1: Timer event forces the output to its active state
350    SetActive = 1,
351}
352impl From<TIMACMP4> for bool {
353    #[inline(always)]
354    fn from(variant: TIMACMP4) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `TIMACMP4` reader - Timer A Compare 4
359pub type TIMACMP4_R = crate::BitReader<TIMACMP4>;
360impl TIMACMP4_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> TIMACMP4 {
364        match self.bits {
365            false => TIMACMP4::NoEffect,
366            true => TIMACMP4::SetActive,
367        }
368    }
369    ///Timer event has no effect
370    #[inline(always)]
371    pub fn is_no_effect(&self) -> bool {
372        *self == TIMACMP4::NoEffect
373    }
374    ///Timer event forces the output to its active state
375    #[inline(always)]
376    pub fn is_set_active(&self) -> bool {
377        *self == TIMACMP4::SetActive
378    }
379}
380///Field `TIMACMP4` writer - Timer A Compare 4
381pub type TIMACMP4_W<'a, REG> = crate::BitWriter<'a, REG, TIMACMP4>;
382impl<'a, REG> TIMACMP4_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///Timer event has no effect
387    #[inline(always)]
388    pub fn no_effect(self) -> &'a mut crate::W<REG> {
389        self.variant(TIMACMP4::NoEffect)
390    }
391    ///Timer event forces the output to its active state
392    #[inline(always)]
393    pub fn set_active(self) -> &'a mut crate::W<REG> {
394        self.variant(TIMACMP4::SetActive)
395    }
396}
397///Field `TIMBCMP3` reader - Timer B Compare 3
398pub use TIMACMP4_R as TIMBCMP3_R;
399///Field `TIMBCMP4` reader - Timer B Compare 4
400pub use TIMACMP4_R as TIMBCMP4_R;
401///Field `TIMCCMP1` reader - Timer C Compare 1
402pub use TIMACMP4_R as TIMCCMP1_R;
403///Field `TIMCCMP2` reader - Timer C Compare 2
404pub use TIMACMP4_R as TIMCCMP2_R;
405///Field `TIMDCMP1` reader - Timer D Compare 1
406pub use TIMACMP4_R as TIMDCMP1_R;
407///Field `TIMDCMP2` reader - Timer D Compare 2
408pub use TIMACMP4_R as TIMDCMP2_R;
409///Field `TIMFCMP3` reader - Timer F Compare 3
410pub use TIMACMP4_R as TIMFCMP3_R;
411///Field `TIMFCMP4` reader - Timer F Compare 4
412pub use TIMACMP4_R as TIMFCMP4_R;
413///Field `TIMBCMP3` writer - Timer B Compare 3
414pub use TIMACMP4_W as TIMBCMP3_W;
415///Field `TIMBCMP4` writer - Timer B Compare 4
416pub use TIMACMP4_W as TIMBCMP4_W;
417///Field `TIMCCMP1` writer - Timer C Compare 1
418pub use TIMACMP4_W as TIMCCMP1_W;
419///Field `TIMCCMP2` writer - Timer C Compare 2
420pub use TIMACMP4_W as TIMCCMP2_W;
421///Field `TIMDCMP1` writer - Timer D Compare 1
422pub use TIMACMP4_W as TIMDCMP1_W;
423///Field `TIMDCMP2` writer - Timer D Compare 2
424pub use TIMACMP4_W as TIMDCMP2_W;
425///Field `TIMFCMP3` writer - Timer F Compare 3
426pub use TIMACMP4_W as TIMFCMP3_W;
427///Field `TIMFCMP4` writer - Timer F Compare 4
428pub use TIMACMP4_W as TIMFCMP4_W;
429/**External Event %s
430
431Value on reset: 0*/
432#[cfg_attr(feature = "defmt", derive(defmt::Format))]
433#[derive(Clone, Copy, Debug, PartialEq, Eq)]
434pub enum EXTEVNT1 {
435    ///0: External event has no effect
436    NoEffect = 0,
437    ///1: External event forces the output to its active state
438    SetActive = 1,
439}
440impl From<EXTEVNT1> for bool {
441    #[inline(always)]
442    fn from(variant: EXTEVNT1) -> Self {
443        variant as u8 != 0
444    }
445}
446///Field `EXTEVNT(1-10)` reader - External Event %s
447pub type EXTEVNT_R = crate::BitReader<EXTEVNT1>;
448impl EXTEVNT_R {
449    ///Get enumerated values variant
450    #[inline(always)]
451    pub const fn variant(&self) -> EXTEVNT1 {
452        match self.bits {
453            false => EXTEVNT1::NoEffect,
454            true => EXTEVNT1::SetActive,
455        }
456    }
457    ///External event has no effect
458    #[inline(always)]
459    pub fn is_no_effect(&self) -> bool {
460        *self == EXTEVNT1::NoEffect
461    }
462    ///External event forces the output to its active state
463    #[inline(always)]
464    pub fn is_set_active(&self) -> bool {
465        *self == EXTEVNT1::SetActive
466    }
467}
468///Field `EXTEVNT(1-10)` writer - External Event %s
469pub type EXTEVNT_W<'a, REG> = crate::BitWriter<'a, REG, EXTEVNT1>;
470impl<'a, REG> EXTEVNT_W<'a, REG>
471where
472    REG: crate::Writable + crate::RegisterSpec,
473{
474    ///External event has no effect
475    #[inline(always)]
476    pub fn no_effect(self) -> &'a mut crate::W<REG> {
477        self.variant(EXTEVNT1::NoEffect)
478    }
479    ///External event forces the output to its active state
480    #[inline(always)]
481    pub fn set_active(self) -> &'a mut crate::W<REG> {
482        self.variant(EXTEVNT1::SetActive)
483    }
484}
485/**Registers update (transfer preload to active)
486
487Value on reset: 0*/
488#[cfg_attr(feature = "defmt", derive(defmt::Format))]
489#[derive(Clone, Copy, Debug, PartialEq, Eq)]
490pub enum UPDATE {
491    ///0: Register update event has no effect
492    NoEffect = 0,
493    ///1: Register update event forces the output to its active state
494    SetActive = 1,
495}
496impl From<UPDATE> for bool {
497    #[inline(always)]
498    fn from(variant: UPDATE) -> Self {
499        variant as u8 != 0
500    }
501}
502///Field `UPDATE` reader - Registers update (transfer preload to active)
503pub type UPDATE_R = crate::BitReader<UPDATE>;
504impl UPDATE_R {
505    ///Get enumerated values variant
506    #[inline(always)]
507    pub const fn variant(&self) -> UPDATE {
508        match self.bits {
509            false => UPDATE::NoEffect,
510            true => UPDATE::SetActive,
511        }
512    }
513    ///Register update event has no effect
514    #[inline(always)]
515    pub fn is_no_effect(&self) -> bool {
516        *self == UPDATE::NoEffect
517    }
518    ///Register update event forces the output to its active state
519    #[inline(always)]
520    pub fn is_set_active(&self) -> bool {
521        *self == UPDATE::SetActive
522    }
523}
524///Field `UPDATE` writer - Registers update (transfer preload to active)
525pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG, UPDATE>;
526impl<'a, REG> UPDATE_W<'a, REG>
527where
528    REG: crate::Writable + crate::RegisterSpec,
529{
530    ///Register update event has no effect
531    #[inline(always)]
532    pub fn no_effect(self) -> &'a mut crate::W<REG> {
533        self.variant(UPDATE::NoEffect)
534    }
535    ///Register update event forces the output to its active state
536    #[inline(always)]
537    pub fn set_active(self) -> &'a mut crate::W<REG> {
538        self.variant(UPDATE::SetActive)
539    }
540}
541impl R {
542    ///Bit 0 - Software Set trigger
543    #[inline(always)]
544    pub fn sst(&self) -> SST_R {
545        SST_R::new((self.bits & 1) != 0)
546    }
547    ///Bit 1 - Timer A resynchronizaton
548    #[inline(always)]
549    pub fn resync(&self) -> RESYNC_R {
550        RESYNC_R::new(((self.bits >> 1) & 1) != 0)
551    }
552    ///Bit 2 - Timer A Period
553    #[inline(always)]
554    pub fn per(&self) -> PER_R {
555        PER_R::new(((self.bits >> 2) & 1) != 0)
556    }
557    ///Timer A compare (1-4)
558    ///
559    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CMP1` field.</div>
560    #[inline(always)]
561    pub fn cmp(&self, n: u8) -> CMP_R {
562        #[allow(clippy::no_effect)] [(); 4][n as usize];
563        CMP_R::new(((self.bits >> (n + 3)) & 1) != 0)
564    }
565    ///Iterator for array of:
566    ///Timer A compare (1-4)
567    #[inline(always)]
568    pub fn cmp_iter(&self) -> impl Iterator<Item = CMP_R> + '_ {
569        (0..4).map(move |n| CMP_R::new(((self.bits >> (n + 3)) & 1) != 0))
570    }
571    ///Bit 3 - Timer A compare 1
572    #[inline(always)]
573    pub fn cmp1(&self) -> CMP_R {
574        CMP_R::new(((self.bits >> 3) & 1) != 0)
575    }
576    ///Bit 4 - Timer A compare 2
577    #[inline(always)]
578    pub fn cmp2(&self) -> CMP_R {
579        CMP_R::new(((self.bits >> 4) & 1) != 0)
580    }
581    ///Bit 5 - Timer A compare 3
582    #[inline(always)]
583    pub fn cmp3(&self) -> CMP_R {
584        CMP_R::new(((self.bits >> 5) & 1) != 0)
585    }
586    ///Bit 6 - Timer A compare 4
587    #[inline(always)]
588    pub fn cmp4(&self) -> CMP_R {
589        CMP_R::new(((self.bits >> 6) & 1) != 0)
590    }
591    ///Bit 7 - Master Period
592    #[inline(always)]
593    pub fn mstper(&self) -> MSTPER_R {
594        MSTPER_R::new(((self.bits >> 7) & 1) != 0)
595    }
596    ///Master Compare (1-4)
597    ///
598    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MSTCMP1` field.</div>
599    #[inline(always)]
600    pub fn mstcmp(&self, n: u8) -> MSTCMP_R {
601        #[allow(clippy::no_effect)] [(); 4][n as usize];
602        MSTCMP_R::new(((self.bits >> (n + 8)) & 1) != 0)
603    }
604    ///Iterator for array of:
605    ///Master Compare (1-4)
606    #[inline(always)]
607    pub fn mstcmp_iter(&self) -> impl Iterator<Item = MSTCMP_R> + '_ {
608        (0..4).map(move |n| MSTCMP_R::new(((self.bits >> (n + 8)) & 1) != 0))
609    }
610    ///Bit 8 - Master Compare 1
611    #[inline(always)]
612    pub fn mstcmp1(&self) -> MSTCMP_R {
613        MSTCMP_R::new(((self.bits >> 8) & 1) != 0)
614    }
615    ///Bit 9 - Master Compare 2
616    #[inline(always)]
617    pub fn mstcmp2(&self) -> MSTCMP_R {
618        MSTCMP_R::new(((self.bits >> 9) & 1) != 0)
619    }
620    ///Bit 10 - Master Compare 3
621    #[inline(always)]
622    pub fn mstcmp3(&self) -> MSTCMP_R {
623        MSTCMP_R::new(((self.bits >> 10) & 1) != 0)
624    }
625    ///Bit 11 - Master Compare 4
626    #[inline(always)]
627    pub fn mstcmp4(&self) -> MSTCMP_R {
628        MSTCMP_R::new(((self.bits >> 11) & 1) != 0)
629    }
630    ///Bit 12 - Timer A Compare 4
631    #[inline(always)]
632    pub fn timacmp4(&self) -> TIMACMP4_R {
633        TIMACMP4_R::new(((self.bits >> 12) & 1) != 0)
634    }
635    ///Bit 13 - Timer B Compare 3
636    #[inline(always)]
637    pub fn timbcmp3(&self) -> TIMBCMP3_R {
638        TIMBCMP3_R::new(((self.bits >> 13) & 1) != 0)
639    }
640    ///Bit 14 - Timer B Compare 4
641    #[inline(always)]
642    pub fn timbcmp4(&self) -> TIMBCMP4_R {
643        TIMBCMP4_R::new(((self.bits >> 14) & 1) != 0)
644    }
645    ///Bit 15 - Timer C Compare 1
646    #[inline(always)]
647    pub fn timccmp1(&self) -> TIMCCMP1_R {
648        TIMCCMP1_R::new(((self.bits >> 15) & 1) != 0)
649    }
650    ///Bit 16 - Timer C Compare 2
651    #[inline(always)]
652    pub fn timccmp2(&self) -> TIMCCMP2_R {
653        TIMCCMP2_R::new(((self.bits >> 16) & 1) != 0)
654    }
655    ///Bit 17 - Timer D Compare 1
656    #[inline(always)]
657    pub fn timdcmp1(&self) -> TIMDCMP1_R {
658        TIMDCMP1_R::new(((self.bits >> 17) & 1) != 0)
659    }
660    ///Bit 18 - Timer D Compare 2
661    #[inline(always)]
662    pub fn timdcmp2(&self) -> TIMDCMP2_R {
663        TIMDCMP2_R::new(((self.bits >> 18) & 1) != 0)
664    }
665    ///Bit 19 - Timer F Compare 3
666    #[inline(always)]
667    pub fn timfcmp3(&self) -> TIMFCMP3_R {
668        TIMFCMP3_R::new(((self.bits >> 19) & 1) != 0)
669    }
670    ///Bit 20 - Timer F Compare 4
671    #[inline(always)]
672    pub fn timfcmp4(&self) -> TIMFCMP4_R {
673        TIMFCMP4_R::new(((self.bits >> 20) & 1) != 0)
674    }
675    ///External Event (1-10)
676    ///
677    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EXTEVNT1` field.</div>
678    #[inline(always)]
679    pub fn extevnt(&self, n: u8) -> EXTEVNT_R {
680        #[allow(clippy::no_effect)] [(); 10][n as usize];
681        EXTEVNT_R::new(((self.bits >> (n + 21)) & 1) != 0)
682    }
683    ///Iterator for array of:
684    ///External Event (1-10)
685    #[inline(always)]
686    pub fn extevnt_iter(&self) -> impl Iterator<Item = EXTEVNT_R> + '_ {
687        (0..10).map(move |n| EXTEVNT_R::new(((self.bits >> (n + 21)) & 1) != 0))
688    }
689    ///Bit 21 - External Event 1
690    #[inline(always)]
691    pub fn extevnt1(&self) -> EXTEVNT_R {
692        EXTEVNT_R::new(((self.bits >> 21) & 1) != 0)
693    }
694    ///Bit 22 - External Event 2
695    #[inline(always)]
696    pub fn extevnt2(&self) -> EXTEVNT_R {
697        EXTEVNT_R::new(((self.bits >> 22) & 1) != 0)
698    }
699    ///Bit 23 - External Event 3
700    #[inline(always)]
701    pub fn extevnt3(&self) -> EXTEVNT_R {
702        EXTEVNT_R::new(((self.bits >> 23) & 1) != 0)
703    }
704    ///Bit 24 - External Event 4
705    #[inline(always)]
706    pub fn extevnt4(&self) -> EXTEVNT_R {
707        EXTEVNT_R::new(((self.bits >> 24) & 1) != 0)
708    }
709    ///Bit 25 - External Event 5
710    #[inline(always)]
711    pub fn extevnt5(&self) -> EXTEVNT_R {
712        EXTEVNT_R::new(((self.bits >> 25) & 1) != 0)
713    }
714    ///Bit 26 - External Event 6
715    #[inline(always)]
716    pub fn extevnt6(&self) -> EXTEVNT_R {
717        EXTEVNT_R::new(((self.bits >> 26) & 1) != 0)
718    }
719    ///Bit 27 - External Event 7
720    #[inline(always)]
721    pub fn extevnt7(&self) -> EXTEVNT_R {
722        EXTEVNT_R::new(((self.bits >> 27) & 1) != 0)
723    }
724    ///Bit 28 - External Event 8
725    #[inline(always)]
726    pub fn extevnt8(&self) -> EXTEVNT_R {
727        EXTEVNT_R::new(((self.bits >> 28) & 1) != 0)
728    }
729    ///Bit 29 - External Event 9
730    #[inline(always)]
731    pub fn extevnt9(&self) -> EXTEVNT_R {
732        EXTEVNT_R::new(((self.bits >> 29) & 1) != 0)
733    }
734    ///Bit 30 - External Event 10
735    #[inline(always)]
736    pub fn extevnt10(&self) -> EXTEVNT_R {
737        EXTEVNT_R::new(((self.bits >> 30) & 1) != 0)
738    }
739    ///Bit 31 - Registers update (transfer preload to active)
740    #[inline(always)]
741    pub fn update(&self) -> UPDATE_R {
742        UPDATE_R::new(((self.bits >> 31) & 1) != 0)
743    }
744}
745impl core::fmt::Debug for R {
746    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
747        f.debug_struct("SET1R")
748            .field("update", &self.update())
749            .field("extevnt1", &self.extevnt1())
750            .field("extevnt2", &self.extevnt2())
751            .field("extevnt3", &self.extevnt3())
752            .field("extevnt4", &self.extevnt4())
753            .field("extevnt5", &self.extevnt5())
754            .field("extevnt6", &self.extevnt6())
755            .field("extevnt7", &self.extevnt7())
756            .field("extevnt8", &self.extevnt8())
757            .field("extevnt9", &self.extevnt9())
758            .field("extevnt10", &self.extevnt10())
759            .field("timacmp4", &self.timacmp4())
760            .field("timfcmp4", &self.timfcmp4())
761            .field("timfcmp3", &self.timfcmp3())
762            .field("timdcmp2", &self.timdcmp2())
763            .field("timdcmp1", &self.timdcmp1())
764            .field("timccmp2", &self.timccmp2())
765            .field("timccmp1", &self.timccmp1())
766            .field("timbcmp4", &self.timbcmp4())
767            .field("timbcmp3", &self.timbcmp3())
768            .field("mstcmp1", &self.mstcmp1())
769            .field("mstcmp2", &self.mstcmp2())
770            .field("mstcmp3", &self.mstcmp3())
771            .field("mstcmp4", &self.mstcmp4())
772            .field("mstper", &self.mstper())
773            .field("cmp1", &self.cmp1())
774            .field("cmp2", &self.cmp2())
775            .field("cmp3", &self.cmp3())
776            .field("cmp4", &self.cmp4())
777            .field("per", &self.per())
778            .field("resync", &self.resync())
779            .field("sst", &self.sst())
780            .finish()
781    }
782}
783impl W {
784    ///Bit 0 - Software Set trigger
785    #[inline(always)]
786    pub fn sst(&mut self) -> SST_W<SET1Rrs> {
787        SST_W::new(self, 0)
788    }
789    ///Bit 1 - Timer A resynchronizaton
790    #[inline(always)]
791    pub fn resync(&mut self) -> RESYNC_W<SET1Rrs> {
792        RESYNC_W::new(self, 1)
793    }
794    ///Bit 2 - Timer A Period
795    #[inline(always)]
796    pub fn per(&mut self) -> PER_W<SET1Rrs> {
797        PER_W::new(self, 2)
798    }
799    ///Timer A compare (1-4)
800    ///
801    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CMP1` field.</div>
802    #[inline(always)]
803    pub fn cmp(&mut self, n: u8) -> CMP_W<SET1Rrs> {
804        #[allow(clippy::no_effect)] [(); 4][n as usize];
805        CMP_W::new(self, n + 3)
806    }
807    ///Bit 3 - Timer A compare 1
808    #[inline(always)]
809    pub fn cmp1(&mut self) -> CMP_W<SET1Rrs> {
810        CMP_W::new(self, 3)
811    }
812    ///Bit 4 - Timer A compare 2
813    #[inline(always)]
814    pub fn cmp2(&mut self) -> CMP_W<SET1Rrs> {
815        CMP_W::new(self, 4)
816    }
817    ///Bit 5 - Timer A compare 3
818    #[inline(always)]
819    pub fn cmp3(&mut self) -> CMP_W<SET1Rrs> {
820        CMP_W::new(self, 5)
821    }
822    ///Bit 6 - Timer A compare 4
823    #[inline(always)]
824    pub fn cmp4(&mut self) -> CMP_W<SET1Rrs> {
825        CMP_W::new(self, 6)
826    }
827    ///Bit 7 - Master Period
828    #[inline(always)]
829    pub fn mstper(&mut self) -> MSTPER_W<SET1Rrs> {
830        MSTPER_W::new(self, 7)
831    }
832    ///Master Compare (1-4)
833    ///
834    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MSTCMP1` field.</div>
835    #[inline(always)]
836    pub fn mstcmp(&mut self, n: u8) -> MSTCMP_W<SET1Rrs> {
837        #[allow(clippy::no_effect)] [(); 4][n as usize];
838        MSTCMP_W::new(self, n + 8)
839    }
840    ///Bit 8 - Master Compare 1
841    #[inline(always)]
842    pub fn mstcmp1(&mut self) -> MSTCMP_W<SET1Rrs> {
843        MSTCMP_W::new(self, 8)
844    }
845    ///Bit 9 - Master Compare 2
846    #[inline(always)]
847    pub fn mstcmp2(&mut self) -> MSTCMP_W<SET1Rrs> {
848        MSTCMP_W::new(self, 9)
849    }
850    ///Bit 10 - Master Compare 3
851    #[inline(always)]
852    pub fn mstcmp3(&mut self) -> MSTCMP_W<SET1Rrs> {
853        MSTCMP_W::new(self, 10)
854    }
855    ///Bit 11 - Master Compare 4
856    #[inline(always)]
857    pub fn mstcmp4(&mut self) -> MSTCMP_W<SET1Rrs> {
858        MSTCMP_W::new(self, 11)
859    }
860    ///Bit 12 - Timer A Compare 4
861    #[inline(always)]
862    pub fn timacmp4(&mut self) -> TIMACMP4_W<SET1Rrs> {
863        TIMACMP4_W::new(self, 12)
864    }
865    ///Bit 13 - Timer B Compare 3
866    #[inline(always)]
867    pub fn timbcmp3(&mut self) -> TIMBCMP3_W<SET1Rrs> {
868        TIMBCMP3_W::new(self, 13)
869    }
870    ///Bit 14 - Timer B Compare 4
871    #[inline(always)]
872    pub fn timbcmp4(&mut self) -> TIMBCMP4_W<SET1Rrs> {
873        TIMBCMP4_W::new(self, 14)
874    }
875    ///Bit 15 - Timer C Compare 1
876    #[inline(always)]
877    pub fn timccmp1(&mut self) -> TIMCCMP1_W<SET1Rrs> {
878        TIMCCMP1_W::new(self, 15)
879    }
880    ///Bit 16 - Timer C Compare 2
881    #[inline(always)]
882    pub fn timccmp2(&mut self) -> TIMCCMP2_W<SET1Rrs> {
883        TIMCCMP2_W::new(self, 16)
884    }
885    ///Bit 17 - Timer D Compare 1
886    #[inline(always)]
887    pub fn timdcmp1(&mut self) -> TIMDCMP1_W<SET1Rrs> {
888        TIMDCMP1_W::new(self, 17)
889    }
890    ///Bit 18 - Timer D Compare 2
891    #[inline(always)]
892    pub fn timdcmp2(&mut self) -> TIMDCMP2_W<SET1Rrs> {
893        TIMDCMP2_W::new(self, 18)
894    }
895    ///Bit 19 - Timer F Compare 3
896    #[inline(always)]
897    pub fn timfcmp3(&mut self) -> TIMFCMP3_W<SET1Rrs> {
898        TIMFCMP3_W::new(self, 19)
899    }
900    ///Bit 20 - Timer F Compare 4
901    #[inline(always)]
902    pub fn timfcmp4(&mut self) -> TIMFCMP4_W<SET1Rrs> {
903        TIMFCMP4_W::new(self, 20)
904    }
905    ///External Event (1-10)
906    ///
907    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `EXTEVNT1` field.</div>
908    #[inline(always)]
909    pub fn extevnt(&mut self, n: u8) -> EXTEVNT_W<SET1Rrs> {
910        #[allow(clippy::no_effect)] [(); 10][n as usize];
911        EXTEVNT_W::new(self, n + 21)
912    }
913    ///Bit 21 - External Event 1
914    #[inline(always)]
915    pub fn extevnt1(&mut self) -> EXTEVNT_W<SET1Rrs> {
916        EXTEVNT_W::new(self, 21)
917    }
918    ///Bit 22 - External Event 2
919    #[inline(always)]
920    pub fn extevnt2(&mut self) -> EXTEVNT_W<SET1Rrs> {
921        EXTEVNT_W::new(self, 22)
922    }
923    ///Bit 23 - External Event 3
924    #[inline(always)]
925    pub fn extevnt3(&mut self) -> EXTEVNT_W<SET1Rrs> {
926        EXTEVNT_W::new(self, 23)
927    }
928    ///Bit 24 - External Event 4
929    #[inline(always)]
930    pub fn extevnt4(&mut self) -> EXTEVNT_W<SET1Rrs> {
931        EXTEVNT_W::new(self, 24)
932    }
933    ///Bit 25 - External Event 5
934    #[inline(always)]
935    pub fn extevnt5(&mut self) -> EXTEVNT_W<SET1Rrs> {
936        EXTEVNT_W::new(self, 25)
937    }
938    ///Bit 26 - External Event 6
939    #[inline(always)]
940    pub fn extevnt6(&mut self) -> EXTEVNT_W<SET1Rrs> {
941        EXTEVNT_W::new(self, 26)
942    }
943    ///Bit 27 - External Event 7
944    #[inline(always)]
945    pub fn extevnt7(&mut self) -> EXTEVNT_W<SET1Rrs> {
946        EXTEVNT_W::new(self, 27)
947    }
948    ///Bit 28 - External Event 8
949    #[inline(always)]
950    pub fn extevnt8(&mut self) -> EXTEVNT_W<SET1Rrs> {
951        EXTEVNT_W::new(self, 28)
952    }
953    ///Bit 29 - External Event 9
954    #[inline(always)]
955    pub fn extevnt9(&mut self) -> EXTEVNT_W<SET1Rrs> {
956        EXTEVNT_W::new(self, 29)
957    }
958    ///Bit 30 - External Event 10
959    #[inline(always)]
960    pub fn extevnt10(&mut self) -> EXTEVNT_W<SET1Rrs> {
961        EXTEVNT_W::new(self, 30)
962    }
963    ///Bit 31 - Registers update (transfer preload to active)
964    #[inline(always)]
965    pub fn update(&mut self) -> UPDATE_W<SET1Rrs> {
966        UPDATE_W::new(self, 31)
967    }
968}
969/**Timerx Output1 Set Register
970
971You can [`read`](crate::Reg::read) this register and get [`set1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
972
973See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#HRTIM_TIME:SET1R)*/
974pub struct SET1Rrs;
975impl crate::RegisterSpec for SET1Rrs {
976    type Ux = u32;
977}
978///`read()` method returns [`set1r::R`](R) reader structure
979impl crate::Readable for SET1Rrs {}
980///`write(|w| ..)` method takes [`set1r::W`](W) writer structure
981impl crate::Writable for SET1Rrs {
982    type Safety = crate::Unsafe;
983}
984///`reset()` method sets SET1R to value 0
985impl crate::Resettable for SET1Rrs {}
stm32g4_staging/stm32g474/hrtim_time/set1r.rs

stm32g4_staging/stm32g474/hrtim_time/
set1r.rs
