stm32g4_staging/stm32g441/ucpd1/
cfgr2.rs

1///Register `CFGR2` reader
2pub type R = crate::R<CFGR2rs>;
3///Register `CFGR2` writer
4pub type W = crate::W<CFGR2rs>;
5/**RXFILTDIS
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RXFILTDIS {
11    ///0: Rx pre-filter enabled
12    Enabled = 0,
13    ///1: Rx pre-filter disabled
14    Disabled = 1,
15}
16impl From<RXFILTDIS> for bool {
17    #[inline(always)]
18    fn from(variant: RXFILTDIS) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `RXFILTDIS` reader - RXFILTDIS
23pub type RXFILTDIS_R = crate::BitReader<RXFILTDIS>;
24impl RXFILTDIS_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RXFILTDIS {
28        match self.bits {
29            false => RXFILTDIS::Enabled,
30            true => RXFILTDIS::Disabled,
31        }
32    }
33    ///Rx pre-filter enabled
34    #[inline(always)]
35    pub fn is_enabled(&self) -> bool {
36        *self == RXFILTDIS::Enabled
37    }
38    ///Rx pre-filter disabled
39    #[inline(always)]
40    pub fn is_disabled(&self) -> bool {
41        *self == RXFILTDIS::Disabled
42    }
43}
44///Field `RXFILTDIS` writer - RXFILTDIS
45pub type RXFILTDIS_W<'a, REG> = crate::BitWriter<'a, REG, RXFILTDIS>;
46impl<'a, REG> RXFILTDIS_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Rx pre-filter enabled
51    #[inline(always)]
52    pub fn enabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RXFILTDIS::Enabled)
54    }
55    ///Rx pre-filter disabled
56    #[inline(always)]
57    pub fn disabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RXFILTDIS::Disabled)
59    }
60}
61/**RXFILT2N3
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum RXFILT2N3 {
67    ///0: 3 samples
68    Samp3 = 0,
69    ///1: 2 samples
70    Samp2 = 1,
71}
72impl From<RXFILT2N3> for bool {
73    #[inline(always)]
74    fn from(variant: RXFILT2N3) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `RXFILT2N3` reader - RXFILT2N3
79pub type RXFILT2N3_R = crate::BitReader<RXFILT2N3>;
80impl RXFILT2N3_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> RXFILT2N3 {
84        match self.bits {
85            false => RXFILT2N3::Samp3,
86            true => RXFILT2N3::Samp2,
87        }
88    }
89    ///3 samples
90    #[inline(always)]
91    pub fn is_samp3(&self) -> bool {
92        *self == RXFILT2N3::Samp3
93    }
94    ///2 samples
95    #[inline(always)]
96    pub fn is_samp2(&self) -> bool {
97        *self == RXFILT2N3::Samp2
98    }
99}
100///Field `RXFILT2N3` writer - RXFILT2N3
101pub type RXFILT2N3_W<'a, REG> = crate::BitWriter<'a, REG, RXFILT2N3>;
102impl<'a, REG> RXFILT2N3_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///3 samples
107    #[inline(always)]
108    pub fn samp3(self) -> &'a mut crate::W<REG> {
109        self.variant(RXFILT2N3::Samp3)
110    }
111    ///2 samples
112    #[inline(always)]
113    pub fn samp2(self) -> &'a mut crate::W<REG> {
114        self.variant(RXFILT2N3::Samp2)
115    }
116}
117/**FORCECLK
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum FORCECLK {
123    ///0: Do not force clock request
124    NoForce = 0,
125    ///1: Force clock request
126    Force = 1,
127}
128impl From<FORCECLK> for bool {
129    #[inline(always)]
130    fn from(variant: FORCECLK) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `FORCECLK` reader - FORCECLK
135pub type FORCECLK_R = crate::BitReader<FORCECLK>;
136impl FORCECLK_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> FORCECLK {
140        match self.bits {
141            false => FORCECLK::NoForce,
142            true => FORCECLK::Force,
143        }
144    }
145    ///Do not force clock request
146    #[inline(always)]
147    pub fn is_no_force(&self) -> bool {
148        *self == FORCECLK::NoForce
149    }
150    ///Force clock request
151    #[inline(always)]
152    pub fn is_force(&self) -> bool {
153        *self == FORCECLK::Force
154    }
155}
156///Field `FORCECLK` writer - FORCECLK
157pub type FORCECLK_W<'a, REG> = crate::BitWriter<'a, REG, FORCECLK>;
158impl<'a, REG> FORCECLK_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Do not force clock request
163    #[inline(always)]
164    pub fn no_force(self) -> &'a mut crate::W<REG> {
165        self.variant(FORCECLK::NoForce)
166    }
167    ///Force clock request
168    #[inline(always)]
169    pub fn force(self) -> &'a mut crate::W<REG> {
170        self.variant(FORCECLK::Force)
171    }
172}
173/**WUPEN
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum WUPEN {
179    ///0: Disabled
180    Disabled = 0,
181    ///1: Enabled
182    Enabled = 1,
183}
184impl From<WUPEN> for bool {
185    #[inline(always)]
186    fn from(variant: WUPEN) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `WUPEN` reader - WUPEN
191pub type WUPEN_R = crate::BitReader<WUPEN>;
192impl WUPEN_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> WUPEN {
196        match self.bits {
197            false => WUPEN::Disabled,
198            true => WUPEN::Enabled,
199        }
200    }
201    ///Disabled
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == WUPEN::Disabled
205    }
206    ///Enabled
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == WUPEN::Enabled
210    }
211}
212///Field `WUPEN` writer - WUPEN
213pub type WUPEN_W<'a, REG> = crate::BitWriter<'a, REG, WUPEN>;
214impl<'a, REG> WUPEN_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Disabled
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(WUPEN::Disabled)
222    }
223    ///Enabled
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(WUPEN::Enabled)
227    }
228}
229impl R {
230    ///Bit 0 - RXFILTDIS
231    #[inline(always)]
232    pub fn rxfiltdis(&self) -> RXFILTDIS_R {
233        RXFILTDIS_R::new((self.bits & 1) != 0)
234    }
235    ///Bit 1 - RXFILT2N3
236    #[inline(always)]
237    pub fn rxfilt2n3(&self) -> RXFILT2N3_R {
238        RXFILT2N3_R::new(((self.bits >> 1) & 1) != 0)
239    }
240    ///Bit 2 - FORCECLK
241    #[inline(always)]
242    pub fn forceclk(&self) -> FORCECLK_R {
243        FORCECLK_R::new(((self.bits >> 2) & 1) != 0)
244    }
245    ///Bit 3 - WUPEN
246    #[inline(always)]
247    pub fn wupen(&self) -> WUPEN_R {
248        WUPEN_R::new(((self.bits >> 3) & 1) != 0)
249    }
250}
251impl core::fmt::Debug for R {
252    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
253        f.debug_struct("CFGR2")
254            .field("rxfiltdis", &self.rxfiltdis())
255            .field("rxfilt2n3", &self.rxfilt2n3())
256            .field("forceclk", &self.forceclk())
257            .field("wupen", &self.wupen())
258            .finish()
259    }
260}
261impl W {
262    ///Bit 0 - RXFILTDIS
263    #[inline(always)]
264    pub fn rxfiltdis(&mut self) -> RXFILTDIS_W<CFGR2rs> {
265        RXFILTDIS_W::new(self, 0)
266    }
267    ///Bit 1 - RXFILT2N3
268    #[inline(always)]
269    pub fn rxfilt2n3(&mut self) -> RXFILT2N3_W<CFGR2rs> {
270        RXFILT2N3_W::new(self, 1)
271    }
272    ///Bit 2 - FORCECLK
273    #[inline(always)]
274    pub fn forceclk(&mut self) -> FORCECLK_W<CFGR2rs> {
275        FORCECLK_W::new(self, 2)
276    }
277    ///Bit 3 - WUPEN
278    #[inline(always)]
279    pub fn wupen(&mut self) -> WUPEN_W<CFGR2rs> {
280        WUPEN_W::new(self, 3)
281    }
282}
283/**UCPD configuration register 2
284
285You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
286
287See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#UCPD1:CFGR2)*/
288pub struct CFGR2rs;
289impl crate::RegisterSpec for CFGR2rs {
290    type Ux = u32;
291}
292///`read()` method returns [`cfgr2::R`](R) reader structure
293impl crate::Readable for CFGR2rs {}
294///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
295impl crate::Writable for CFGR2rs {
296    type Safety = crate::Unsafe;
297}
298///`reset()` method sets CFGR2 to value 0
299impl crate::Resettable for CFGR2rs {}
stm32g4_staging/stm32g441/ucpd1/cfgr2.rs

stm32g4_staging/stm32g441/ucpd1/
cfgr2.rs
