stm32g4_staging/stm32g484/fdcan/
xidam.rs

1///Register `XIDAM` reader
2pub type R = crate::R<XIDAMrs>;
3///Register `XIDAM` writer
4pub type W = crate::W<XIDAMrs>;
5///Field `EIDM` reader - Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
6pub type EIDM_R = crate::FieldReader<u32>;
7///Field `EIDM` writer - Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
8pub type EIDM_W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
9impl R {
10    ///Bits 0:28 - Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
11    #[inline(always)]
12    pub fn eidm(&self) -> EIDM_R {
13        EIDM_R::new(self.bits & 0x1fff_ffff)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("XIDAM").field("eidm", &self.eidm()).finish()
19    }
20}
21impl W {
22    ///Bits 0:28 - Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
23    #[inline(always)]
24    pub fn eidm(&mut self) -> EIDM_W<XIDAMrs> {
25        EIDM_W::new(self, 0)
26    }
27}
28/**FDCAN extended ID and mask register
29
30You can [`read`](crate::Reg::read) this register and get [`xidam::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xidam::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
31
32See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FDCAN:XIDAM)*/
33pub struct XIDAMrs;
34impl crate::RegisterSpec for XIDAMrs {
35    type Ux = u32;
36}
37///`read()` method returns [`xidam::R`](R) reader structure
38impl crate::Readable for XIDAMrs {}
39///`write(|w| ..)` method takes [`xidam::W`](W) writer structure
40impl crate::Writable for XIDAMrs {
41    type Safety = crate::Unsafe;
42}
43///`reset()` method sets XIDAM to value 0x1fff_ffff
44impl crate::Resettable for XIDAMrs {
45    const RESET_VALUE: u32 = 0x1fff_ffff;
46}
stm32g4_staging/stm32g484/fdcan/xidam.rs

stm32g4_staging/stm32g484/fdcan/
xidam.rs
