stm32g4_staging/stm32g484/exti/
imr1.rs

1///Register `IMR1` reader
2pub type R = crate::R<IMR1rs>;
3///Register `IMR1` writer
4pub type W = crate::W<IMR1rs>;
5/**Interrupt Mask on line 0
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum INTERRUPT_MASK {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<INTERRUPT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: INTERRUPT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `IM0` reader - Interrupt Mask on line 0
23pub type IM0_R = crate::BitReader<INTERRUPT_MASK>;
24impl IM0_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> INTERRUPT_MASK {
28        match self.bits {
29            false => INTERRUPT_MASK::Masked,
30            true => INTERRUPT_MASK::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == INTERRUPT_MASK::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == INTERRUPT_MASK::Unmasked
42    }
43}
44///Field `IM0` writer - Interrupt Mask on line 0
45pub type IM0_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_MASK>;
46impl<'a, REG> IM0_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(INTERRUPT_MASK::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(INTERRUPT_MASK::Unmasked)
59    }
60}
61///Field `IM1` reader - Interrupt Mask on line 1
62pub use IM0_R as IM1_R;
63///Field `IM2` reader - Interrupt Mask on line 2
64pub use IM0_R as IM2_R;
65///Field `IM3` reader - Interrupt Mask on line 3
66pub use IM0_R as IM3_R;
67///Field `IM4` reader - Interrupt Mask on line 4
68pub use IM0_R as IM4_R;
69///Field `IM5` reader - Interrupt Mask on line 5
70pub use IM0_R as IM5_R;
71///Field `IM6` reader - Interrupt Mask on line 6
72pub use IM0_R as IM6_R;
73///Field `IM7` reader - Interrupt Mask on line 7
74pub use IM0_R as IM7_R;
75///Field `IM8` reader - Interrupt Mask on line 8
76pub use IM0_R as IM8_R;
77///Field `IM9` reader - Interrupt Mask on line 9
78pub use IM0_R as IM9_R;
79///Field `IM10` reader - Interrupt Mask on line 10
80pub use IM0_R as IM10_R;
81///Field `IM11` reader - Interrupt Mask on line 11
82pub use IM0_R as IM11_R;
83///Field `IM12` reader - Interrupt Mask on line 12
84pub use IM0_R as IM12_R;
85///Field `IM13` reader - Interrupt Mask on line 13
86pub use IM0_R as IM13_R;
87///Field `IM14` reader - Interrupt Mask on line 14
88pub use IM0_R as IM14_R;
89///Field `IM15` reader - Interrupt Mask on line 15
90pub use IM0_R as IM15_R;
91///Field `IM16` reader - Interrupt Mask on line 16
92pub use IM0_R as IM16_R;
93///Field `IM17` reader - Interrupt Mask on line 17
94pub use IM0_R as IM17_R;
95///Field `IM18` reader - Interrupt Mask on line 18
96pub use IM0_R as IM18_R;
97///Field `IM19` reader - Interrupt Mask on line 19
98pub use IM0_R as IM19_R;
99///Field `IM20` reader - Interrupt Mask on line 20
100pub use IM0_R as IM20_R;
101///Field `IM21` reader - Interrupt Mask on line 21
102pub use IM0_R as IM21_R;
103///Field `IM22` reader - Interrupt Mask on line 22
104pub use IM0_R as IM22_R;
105///Field `IM23` reader - Interrupt Mask on line 23
106pub use IM0_R as IM23_R;
107///Field `IM24` reader - Interrupt Mask on line 24
108pub use IM0_R as IM24_R;
109///Field `IM25` reader - Interrupt Mask on line 25
110pub use IM0_R as IM25_R;
111///Field `IM26` reader - Interrupt Mask on line 26
112pub use IM0_R as IM26_R;
113///Field `IM27` reader - Interrupt Mask on line 27
114pub use IM0_R as IM27_R;
115///Field `IM28` reader - Interrupt Mask on line 28
116pub use IM0_R as IM28_R;
117///Field `IM29` reader - Interrupt Mask on line 29
118pub use IM0_R as IM29_R;
119///Field `IM30` reader - Interrupt Mask on line 30
120pub use IM0_R as IM30_R;
121///Field `IM31` reader - Interrupt Mask on line 31
122pub use IM0_R as IM31_R;
123///Field `IM1` writer - Interrupt Mask on line 1
124pub use IM0_W as IM1_W;
125///Field `IM2` writer - Interrupt Mask on line 2
126pub use IM0_W as IM2_W;
127///Field `IM3` writer - Interrupt Mask on line 3
128pub use IM0_W as IM3_W;
129///Field `IM4` writer - Interrupt Mask on line 4
130pub use IM0_W as IM4_W;
131///Field `IM5` writer - Interrupt Mask on line 5
132pub use IM0_W as IM5_W;
133///Field `IM6` writer - Interrupt Mask on line 6
134pub use IM0_W as IM6_W;
135///Field `IM7` writer - Interrupt Mask on line 7
136pub use IM0_W as IM7_W;
137///Field `IM8` writer - Interrupt Mask on line 8
138pub use IM0_W as IM8_W;
139///Field `IM9` writer - Interrupt Mask on line 9
140pub use IM0_W as IM9_W;
141///Field `IM10` writer - Interrupt Mask on line 10
142pub use IM0_W as IM10_W;
143///Field `IM11` writer - Interrupt Mask on line 11
144pub use IM0_W as IM11_W;
145///Field `IM12` writer - Interrupt Mask on line 12
146pub use IM0_W as IM12_W;
147///Field `IM13` writer - Interrupt Mask on line 13
148pub use IM0_W as IM13_W;
149///Field `IM14` writer - Interrupt Mask on line 14
150pub use IM0_W as IM14_W;
151///Field `IM15` writer - Interrupt Mask on line 15
152pub use IM0_W as IM15_W;
153///Field `IM16` writer - Interrupt Mask on line 16
154pub use IM0_W as IM16_W;
155///Field `IM17` writer - Interrupt Mask on line 17
156pub use IM0_W as IM17_W;
157///Field `IM18` writer - Interrupt Mask on line 18
158pub use IM0_W as IM18_W;
159///Field `IM19` writer - Interrupt Mask on line 19
160pub use IM0_W as IM19_W;
161///Field `IM20` writer - Interrupt Mask on line 20
162pub use IM0_W as IM20_W;
163///Field `IM21` writer - Interrupt Mask on line 21
164pub use IM0_W as IM21_W;
165///Field `IM22` writer - Interrupt Mask on line 22
166pub use IM0_W as IM22_W;
167///Field `IM23` writer - Interrupt Mask on line 23
168pub use IM0_W as IM23_W;
169///Field `IM24` writer - Interrupt Mask on line 24
170pub use IM0_W as IM24_W;
171///Field `IM25` writer - Interrupt Mask on line 25
172pub use IM0_W as IM25_W;
173///Field `IM26` writer - Interrupt Mask on line 26
174pub use IM0_W as IM26_W;
175///Field `IM27` writer - Interrupt Mask on line 27
176pub use IM0_W as IM27_W;
177///Field `IM28` writer - Interrupt Mask on line 28
178pub use IM0_W as IM28_W;
179///Field `IM29` writer - Interrupt Mask on line 29
180pub use IM0_W as IM29_W;
181///Field `IM30` writer - Interrupt Mask on line 30
182pub use IM0_W as IM30_W;
183///Field `IM31` writer - Interrupt Mask on line 31
184pub use IM0_W as IM31_W;
185impl R {
186    ///Bit 0 - Interrupt Mask on line 0
187    #[inline(always)]
188    pub fn im0(&self) -> IM0_R {
189        IM0_R::new((self.bits & 1) != 0)
190    }
191    ///Bit 1 - Interrupt Mask on line 1
192    #[inline(always)]
193    pub fn im1(&self) -> IM1_R {
194        IM1_R::new(((self.bits >> 1) & 1) != 0)
195    }
196    ///Bit 2 - Interrupt Mask on line 2
197    #[inline(always)]
198    pub fn im2(&self) -> IM2_R {
199        IM2_R::new(((self.bits >> 2) & 1) != 0)
200    }
201    ///Bit 3 - Interrupt Mask on line 3
202    #[inline(always)]
203    pub fn im3(&self) -> IM3_R {
204        IM3_R::new(((self.bits >> 3) & 1) != 0)
205    }
206    ///Bit 4 - Interrupt Mask on line 4
207    #[inline(always)]
208    pub fn im4(&self) -> IM4_R {
209        IM4_R::new(((self.bits >> 4) & 1) != 0)
210    }
211    ///Bit 5 - Interrupt Mask on line 5
212    #[inline(always)]
213    pub fn im5(&self) -> IM5_R {
214        IM5_R::new(((self.bits >> 5) & 1) != 0)
215    }
216    ///Bit 6 - Interrupt Mask on line 6
217    #[inline(always)]
218    pub fn im6(&self) -> IM6_R {
219        IM6_R::new(((self.bits >> 6) & 1) != 0)
220    }
221    ///Bit 7 - Interrupt Mask on line 7
222    #[inline(always)]
223    pub fn im7(&self) -> IM7_R {
224        IM7_R::new(((self.bits >> 7) & 1) != 0)
225    }
226    ///Bit 8 - Interrupt Mask on line 8
227    #[inline(always)]
228    pub fn im8(&self) -> IM8_R {
229        IM8_R::new(((self.bits >> 8) & 1) != 0)
230    }
231    ///Bit 9 - Interrupt Mask on line 9
232    #[inline(always)]
233    pub fn im9(&self) -> IM9_R {
234        IM9_R::new(((self.bits >> 9) & 1) != 0)
235    }
236    ///Bit 10 - Interrupt Mask on line 10
237    #[inline(always)]
238    pub fn im10(&self) -> IM10_R {
239        IM10_R::new(((self.bits >> 10) & 1) != 0)
240    }
241    ///Bit 11 - Interrupt Mask on line 11
242    #[inline(always)]
243    pub fn im11(&self) -> IM11_R {
244        IM11_R::new(((self.bits >> 11) & 1) != 0)
245    }
246    ///Bit 12 - Interrupt Mask on line 12
247    #[inline(always)]
248    pub fn im12(&self) -> IM12_R {
249        IM12_R::new(((self.bits >> 12) & 1) != 0)
250    }
251    ///Bit 13 - Interrupt Mask on line 13
252    #[inline(always)]
253    pub fn im13(&self) -> IM13_R {
254        IM13_R::new(((self.bits >> 13) & 1) != 0)
255    }
256    ///Bit 14 - Interrupt Mask on line 14
257    #[inline(always)]
258    pub fn im14(&self) -> IM14_R {
259        IM14_R::new(((self.bits >> 14) & 1) != 0)
260    }
261    ///Bit 15 - Interrupt Mask on line 15
262    #[inline(always)]
263    pub fn im15(&self) -> IM15_R {
264        IM15_R::new(((self.bits >> 15) & 1) != 0)
265    }
266    ///Bit 16 - Interrupt Mask on line 16
267    #[inline(always)]
268    pub fn im16(&self) -> IM16_R {
269        IM16_R::new(((self.bits >> 16) & 1) != 0)
270    }
271    ///Bit 17 - Interrupt Mask on line 17
272    #[inline(always)]
273    pub fn im17(&self) -> IM17_R {
274        IM17_R::new(((self.bits >> 17) & 1) != 0)
275    }
276    ///Bit 18 - Interrupt Mask on line 18
277    #[inline(always)]
278    pub fn im18(&self) -> IM18_R {
279        IM18_R::new(((self.bits >> 18) & 1) != 0)
280    }
281    ///Bit 19 - Interrupt Mask on line 19
282    #[inline(always)]
283    pub fn im19(&self) -> IM19_R {
284        IM19_R::new(((self.bits >> 19) & 1) != 0)
285    }
286    ///Bit 20 - Interrupt Mask on line 20
287    #[inline(always)]
288    pub fn im20(&self) -> IM20_R {
289        IM20_R::new(((self.bits >> 20) & 1) != 0)
290    }
291    ///Bit 21 - Interrupt Mask on line 21
292    #[inline(always)]
293    pub fn im21(&self) -> IM21_R {
294        IM21_R::new(((self.bits >> 21) & 1) != 0)
295    }
296    ///Bit 22 - Interrupt Mask on line 22
297    #[inline(always)]
298    pub fn im22(&self) -> IM22_R {
299        IM22_R::new(((self.bits >> 22) & 1) != 0)
300    }
301    ///Bit 23 - Interrupt Mask on line 23
302    #[inline(always)]
303    pub fn im23(&self) -> IM23_R {
304        IM23_R::new(((self.bits >> 23) & 1) != 0)
305    }
306    ///Bit 24 - Interrupt Mask on line 24
307    #[inline(always)]
308    pub fn im24(&self) -> IM24_R {
309        IM24_R::new(((self.bits >> 24) & 1) != 0)
310    }
311    ///Bit 25 - Interrupt Mask on line 25
312    #[inline(always)]
313    pub fn im25(&self) -> IM25_R {
314        IM25_R::new(((self.bits >> 25) & 1) != 0)
315    }
316    ///Bit 26 - Interrupt Mask on line 26
317    #[inline(always)]
318    pub fn im26(&self) -> IM26_R {
319        IM26_R::new(((self.bits >> 26) & 1) != 0)
320    }
321    ///Bit 27 - Interrupt Mask on line 27
322    #[inline(always)]
323    pub fn im27(&self) -> IM27_R {
324        IM27_R::new(((self.bits >> 27) & 1) != 0)
325    }
326    ///Bit 28 - Interrupt Mask on line 28
327    #[inline(always)]
328    pub fn im28(&self) -> IM28_R {
329        IM28_R::new(((self.bits >> 28) & 1) != 0)
330    }
331    ///Bit 29 - Interrupt Mask on line 29
332    #[inline(always)]
333    pub fn im29(&self) -> IM29_R {
334        IM29_R::new(((self.bits >> 29) & 1) != 0)
335    }
336    ///Bit 30 - Interrupt Mask on line 30
337    #[inline(always)]
338    pub fn im30(&self) -> IM30_R {
339        IM30_R::new(((self.bits >> 30) & 1) != 0)
340    }
341    ///Bit 31 - Interrupt Mask on line 31
342    #[inline(always)]
343    pub fn im31(&self) -> IM31_R {
344        IM31_R::new(((self.bits >> 31) & 1) != 0)
345    }
346}
347impl core::fmt::Debug for R {
348    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
349        f.debug_struct("IMR1")
350            .field("im0", &self.im0())
351            .field("im1", &self.im1())
352            .field("im2", &self.im2())
353            .field("im3", &self.im3())
354            .field("im4", &self.im4())
355            .field("im5", &self.im5())
356            .field("im6", &self.im6())
357            .field("im7", &self.im7())
358            .field("im8", &self.im8())
359            .field("im9", &self.im9())
360            .field("im10", &self.im10())
361            .field("im11", &self.im11())
362            .field("im12", &self.im12())
363            .field("im13", &self.im13())
364            .field("im14", &self.im14())
365            .field("im15", &self.im15())
366            .field("im16", &self.im16())
367            .field("im17", &self.im17())
368            .field("im18", &self.im18())
369            .field("im19", &self.im19())
370            .field("im20", &self.im20())
371            .field("im21", &self.im21())
372            .field("im22", &self.im22())
373            .field("im23", &self.im23())
374            .field("im24", &self.im24())
375            .field("im25", &self.im25())
376            .field("im26", &self.im26())
377            .field("im27", &self.im27())
378            .field("im28", &self.im28())
379            .field("im29", &self.im29())
380            .field("im30", &self.im30())
381            .field("im31", &self.im31())
382            .finish()
383    }
384}
385impl W {
386    ///Bit 0 - Interrupt Mask on line 0
387    #[inline(always)]
388    pub fn im0(&mut self) -> IM0_W<IMR1rs> {
389        IM0_W::new(self, 0)
390    }
391    ///Bit 1 - Interrupt Mask on line 1
392    #[inline(always)]
393    pub fn im1(&mut self) -> IM1_W<IMR1rs> {
394        IM1_W::new(self, 1)
395    }
396    ///Bit 2 - Interrupt Mask on line 2
397    #[inline(always)]
398    pub fn im2(&mut self) -> IM2_W<IMR1rs> {
399        IM2_W::new(self, 2)
400    }
401    ///Bit 3 - Interrupt Mask on line 3
402    #[inline(always)]
403    pub fn im3(&mut self) -> IM3_W<IMR1rs> {
404        IM3_W::new(self, 3)
405    }
406    ///Bit 4 - Interrupt Mask on line 4
407    #[inline(always)]
408    pub fn im4(&mut self) -> IM4_W<IMR1rs> {
409        IM4_W::new(self, 4)
410    }
411    ///Bit 5 - Interrupt Mask on line 5
412    #[inline(always)]
413    pub fn im5(&mut self) -> IM5_W<IMR1rs> {
414        IM5_W::new(self, 5)
415    }
416    ///Bit 6 - Interrupt Mask on line 6
417    #[inline(always)]
418    pub fn im6(&mut self) -> IM6_W<IMR1rs> {
419        IM6_W::new(self, 6)
420    }
421    ///Bit 7 - Interrupt Mask on line 7
422    #[inline(always)]
423    pub fn im7(&mut self) -> IM7_W<IMR1rs> {
424        IM7_W::new(self, 7)
425    }
426    ///Bit 8 - Interrupt Mask on line 8
427    #[inline(always)]
428    pub fn im8(&mut self) -> IM8_W<IMR1rs> {
429        IM8_W::new(self, 8)
430    }
431    ///Bit 9 - Interrupt Mask on line 9
432    #[inline(always)]
433    pub fn im9(&mut self) -> IM9_W<IMR1rs> {
434        IM9_W::new(self, 9)
435    }
436    ///Bit 10 - Interrupt Mask on line 10
437    #[inline(always)]
438    pub fn im10(&mut self) -> IM10_W<IMR1rs> {
439        IM10_W::new(self, 10)
440    }
441    ///Bit 11 - Interrupt Mask on line 11
442    #[inline(always)]
443    pub fn im11(&mut self) -> IM11_W<IMR1rs> {
444        IM11_W::new(self, 11)
445    }
446    ///Bit 12 - Interrupt Mask on line 12
447    #[inline(always)]
448    pub fn im12(&mut self) -> IM12_W<IMR1rs> {
449        IM12_W::new(self, 12)
450    }
451    ///Bit 13 - Interrupt Mask on line 13
452    #[inline(always)]
453    pub fn im13(&mut self) -> IM13_W<IMR1rs> {
454        IM13_W::new(self, 13)
455    }
456    ///Bit 14 - Interrupt Mask on line 14
457    #[inline(always)]
458    pub fn im14(&mut self) -> IM14_W<IMR1rs> {
459        IM14_W::new(self, 14)
460    }
461    ///Bit 15 - Interrupt Mask on line 15
462    #[inline(always)]
463    pub fn im15(&mut self) -> IM15_W<IMR1rs> {
464        IM15_W::new(self, 15)
465    }
466    ///Bit 16 - Interrupt Mask on line 16
467    #[inline(always)]
468    pub fn im16(&mut self) -> IM16_W<IMR1rs> {
469        IM16_W::new(self, 16)
470    }
471    ///Bit 17 - Interrupt Mask on line 17
472    #[inline(always)]
473    pub fn im17(&mut self) -> IM17_W<IMR1rs> {
474        IM17_W::new(self, 17)
475    }
476    ///Bit 18 - Interrupt Mask on line 18
477    #[inline(always)]
478    pub fn im18(&mut self) -> IM18_W<IMR1rs> {
479        IM18_W::new(self, 18)
480    }
481    ///Bit 19 - Interrupt Mask on line 19
482    #[inline(always)]
483    pub fn im19(&mut self) -> IM19_W<IMR1rs> {
484        IM19_W::new(self, 19)
485    }
486    ///Bit 20 - Interrupt Mask on line 20
487    #[inline(always)]
488    pub fn im20(&mut self) -> IM20_W<IMR1rs> {
489        IM20_W::new(self, 20)
490    }
491    ///Bit 21 - Interrupt Mask on line 21
492    #[inline(always)]
493    pub fn im21(&mut self) -> IM21_W<IMR1rs> {
494        IM21_W::new(self, 21)
495    }
496    ///Bit 22 - Interrupt Mask on line 22
497    #[inline(always)]
498    pub fn im22(&mut self) -> IM22_W<IMR1rs> {
499        IM22_W::new(self, 22)
500    }
501    ///Bit 23 - Interrupt Mask on line 23
502    #[inline(always)]
503    pub fn im23(&mut self) -> IM23_W<IMR1rs> {
504        IM23_W::new(self, 23)
505    }
506    ///Bit 24 - Interrupt Mask on line 24
507    #[inline(always)]
508    pub fn im24(&mut self) -> IM24_W<IMR1rs> {
509        IM24_W::new(self, 24)
510    }
511    ///Bit 25 - Interrupt Mask on line 25
512    #[inline(always)]
513    pub fn im25(&mut self) -> IM25_W<IMR1rs> {
514        IM25_W::new(self, 25)
515    }
516    ///Bit 26 - Interrupt Mask on line 26
517    #[inline(always)]
518    pub fn im26(&mut self) -> IM26_W<IMR1rs> {
519        IM26_W::new(self, 26)
520    }
521    ///Bit 27 - Interrupt Mask on line 27
522    #[inline(always)]
523    pub fn im27(&mut self) -> IM27_W<IMR1rs> {
524        IM27_W::new(self, 27)
525    }
526    ///Bit 28 - Interrupt Mask on line 28
527    #[inline(always)]
528    pub fn im28(&mut self) -> IM28_W<IMR1rs> {
529        IM28_W::new(self, 28)
530    }
531    ///Bit 29 - Interrupt Mask on line 29
532    #[inline(always)]
533    pub fn im29(&mut self) -> IM29_W<IMR1rs> {
534        IM29_W::new(self, 29)
535    }
536    ///Bit 30 - Interrupt Mask on line 30
537    #[inline(always)]
538    pub fn im30(&mut self) -> IM30_W<IMR1rs> {
539        IM30_W::new(self, 30)
540    }
541    ///Bit 31 - Interrupt Mask on line 31
542    #[inline(always)]
543    pub fn im31(&mut self) -> IM31_W<IMR1rs> {
544        IM31_W::new(self, 31)
545    }
546}
547/**Interrupt mask register
548
549You can [`read`](crate::Reg::read) this register and get [`imr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
550
551See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#EXTI:IMR1)*/
552pub struct IMR1rs;
553impl crate::RegisterSpec for IMR1rs {
554    type Ux = u32;
555}
556///`read()` method returns [`imr1::R`](R) reader structure
557impl crate::Readable for IMR1rs {}
558///`write(|w| ..)` method takes [`imr1::W`](W) writer structure
559impl crate::Writable for IMR1rs {
560    type Safety = crate::Unsafe;
561}
562///`reset()` method sets IMR1 to value 0xff82_0000
563impl crate::Resettable for IMR1rs {
564    const RESET_VALUE: u32 = 0xff82_0000;
565}
stm32g4_staging/stm32g484/exti/imr1.rs

stm32g4_staging/stm32g484/exti/
imr1.rs
