stm32g4_staging/stm32g484/exti/
emr1.rs

1///Register `EMR1` reader
2pub type R = crate::R<EMR1rs>;
3///Register `EMR1` writer
4pub type W = crate::W<EMR1rs>;
5/**Event Mask on line 0
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EVENT_MASK {
11    ///0: Event request line is masked
12    Masked = 0,
13    ///1: Event request line is unmasked
14    Unmasked = 1,
15}
16impl From<EVENT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: EVENT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EM0` reader - Event Mask on line 0
23pub type EM0_R = crate::BitReader<EVENT_MASK>;
24impl EM0_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EVENT_MASK {
28        match self.bits {
29            false => EVENT_MASK::Masked,
30            true => EVENT_MASK::Unmasked,
31        }
32    }
33    ///Event request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == EVENT_MASK::Masked
37    }
38    ///Event request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == EVENT_MASK::Unmasked
42    }
43}
44///Field `EM0` writer - Event Mask on line 0
45pub type EM0_W<'a, REG> = crate::BitWriter<'a, REG, EVENT_MASK>;
46impl<'a, REG> EM0_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Event request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(EVENT_MASK::Masked)
54    }
55    ///Event request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(EVENT_MASK::Unmasked)
59    }
60}
61///Field `EM1` reader - Event Mask on line 1
62pub use EM0_R as EM1_R;
63///Field `EM2` reader - Event Mask on line 2
64pub use EM0_R as EM2_R;
65///Field `EM3` reader - Event Mask on line 3
66pub use EM0_R as EM3_R;
67///Field `EM4` reader - Event Mask on line 4
68pub use EM0_R as EM4_R;
69///Field `EM5` reader - Event Mask on line 5
70pub use EM0_R as EM5_R;
71///Field `EM6` reader - Event Mask on line 6
72pub use EM0_R as EM6_R;
73///Field `EM7` reader - Event Mask on line 7
74pub use EM0_R as EM7_R;
75///Field `EM8` reader - Event Mask on line 8
76pub use EM0_R as EM8_R;
77///Field `EM9` reader - Event Mask on line 9
78pub use EM0_R as EM9_R;
79///Field `EM10` reader - Event Mask on line 10
80pub use EM0_R as EM10_R;
81///Field `EM11` reader - Event Mask on line 11
82pub use EM0_R as EM11_R;
83///Field `EM12` reader - Event Mask on line 12
84pub use EM0_R as EM12_R;
85///Field `EM13` reader - Event Mask on line 13
86pub use EM0_R as EM13_R;
87///Field `EM14` reader - Event Mask on line 14
88pub use EM0_R as EM14_R;
89///Field `EM15` reader - Event Mask on line 15
90pub use EM0_R as EM15_R;
91///Field `EM16` reader - Event Mask on line 16
92pub use EM0_R as EM16_R;
93///Field `EM17` reader - Event Mask on line 17
94pub use EM0_R as EM17_R;
95///Field `EM18` reader - Event Mask on line 18
96pub use EM0_R as EM18_R;
97///Field `EM19` reader - Event Mask on line 19
98pub use EM0_R as EM19_R;
99///Field `EM20` reader - Event Mask on line 20
100pub use EM0_R as EM20_R;
101///Field `EM21` reader - Event Mask on line 21
102pub use EM0_R as EM21_R;
103///Field `EM22` reader - Event Mask on line 22
104pub use EM0_R as EM22_R;
105///Field `EM23` reader - Event Mask on line 23
106pub use EM0_R as EM23_R;
107///Field `EM24` reader - Event Mask on line 24
108pub use EM0_R as EM24_R;
109///Field `EM25` reader - Event Mask on line 25
110pub use EM0_R as EM25_R;
111///Field `EM26` reader - Event Mask on line 26
112pub use EM0_R as EM26_R;
113///Field `EM27` reader - Event Mask on line 27
114pub use EM0_R as EM27_R;
115///Field `EM28` reader - Event Mask on line 28
116pub use EM0_R as EM28_R;
117///Field `EM29` reader - Event Mask on line 29
118pub use EM0_R as EM29_R;
119///Field `EM30` reader - Event Mask on line 30
120pub use EM0_R as EM30_R;
121///Field `EM31` reader - Event Mask on line 31
122pub use EM0_R as EM31_R;
123///Field `EM1` writer - Event Mask on line 1
124pub use EM0_W as EM1_W;
125///Field `EM2` writer - Event Mask on line 2
126pub use EM0_W as EM2_W;
127///Field `EM3` writer - Event Mask on line 3
128pub use EM0_W as EM3_W;
129///Field `EM4` writer - Event Mask on line 4
130pub use EM0_W as EM4_W;
131///Field `EM5` writer - Event Mask on line 5
132pub use EM0_W as EM5_W;
133///Field `EM6` writer - Event Mask on line 6
134pub use EM0_W as EM6_W;
135///Field `EM7` writer - Event Mask on line 7
136pub use EM0_W as EM7_W;
137///Field `EM8` writer - Event Mask on line 8
138pub use EM0_W as EM8_W;
139///Field `EM9` writer - Event Mask on line 9
140pub use EM0_W as EM9_W;
141///Field `EM10` writer - Event Mask on line 10
142pub use EM0_W as EM10_W;
143///Field `EM11` writer - Event Mask on line 11
144pub use EM0_W as EM11_W;
145///Field `EM12` writer - Event Mask on line 12
146pub use EM0_W as EM12_W;
147///Field `EM13` writer - Event Mask on line 13
148pub use EM0_W as EM13_W;
149///Field `EM14` writer - Event Mask on line 14
150pub use EM0_W as EM14_W;
151///Field `EM15` writer - Event Mask on line 15
152pub use EM0_W as EM15_W;
153///Field `EM16` writer - Event Mask on line 16
154pub use EM0_W as EM16_W;
155///Field `EM17` writer - Event Mask on line 17
156pub use EM0_W as EM17_W;
157///Field `EM18` writer - Event Mask on line 18
158pub use EM0_W as EM18_W;
159///Field `EM19` writer - Event Mask on line 19
160pub use EM0_W as EM19_W;
161///Field `EM20` writer - Event Mask on line 20
162pub use EM0_W as EM20_W;
163///Field `EM21` writer - Event Mask on line 21
164pub use EM0_W as EM21_W;
165///Field `EM22` writer - Event Mask on line 22
166pub use EM0_W as EM22_W;
167///Field `EM23` writer - Event Mask on line 23
168pub use EM0_W as EM23_W;
169///Field `EM24` writer - Event Mask on line 24
170pub use EM0_W as EM24_W;
171///Field `EM25` writer - Event Mask on line 25
172pub use EM0_W as EM25_W;
173///Field `EM26` writer - Event Mask on line 26
174pub use EM0_W as EM26_W;
175///Field `EM27` writer - Event Mask on line 27
176pub use EM0_W as EM27_W;
177///Field `EM28` writer - Event Mask on line 28
178pub use EM0_W as EM28_W;
179///Field `EM29` writer - Event Mask on line 29
180pub use EM0_W as EM29_W;
181///Field `EM30` writer - Event Mask on line 30
182pub use EM0_W as EM30_W;
183///Field `EM31` writer - Event Mask on line 31
184pub use EM0_W as EM31_W;
185impl R {
186    ///Bit 0 - Event Mask on line 0
187    #[inline(always)]
188    pub fn em0(&self) -> EM0_R {
189        EM0_R::new((self.bits & 1) != 0)
190    }
191    ///Bit 1 - Event Mask on line 1
192    #[inline(always)]
193    pub fn em1(&self) -> EM1_R {
194        EM1_R::new(((self.bits >> 1) & 1) != 0)
195    }
196    ///Bit 2 - Event Mask on line 2
197    #[inline(always)]
198    pub fn em2(&self) -> EM2_R {
199        EM2_R::new(((self.bits >> 2) & 1) != 0)
200    }
201    ///Bit 3 - Event Mask on line 3
202    #[inline(always)]
203    pub fn em3(&self) -> EM3_R {
204        EM3_R::new(((self.bits >> 3) & 1) != 0)
205    }
206    ///Bit 4 - Event Mask on line 4
207    #[inline(always)]
208    pub fn em4(&self) -> EM4_R {
209        EM4_R::new(((self.bits >> 4) & 1) != 0)
210    }
211    ///Bit 5 - Event Mask on line 5
212    #[inline(always)]
213    pub fn em5(&self) -> EM5_R {
214        EM5_R::new(((self.bits >> 5) & 1) != 0)
215    }
216    ///Bit 6 - Event Mask on line 6
217    #[inline(always)]
218    pub fn em6(&self) -> EM6_R {
219        EM6_R::new(((self.bits >> 6) & 1) != 0)
220    }
221    ///Bit 7 - Event Mask on line 7
222    #[inline(always)]
223    pub fn em7(&self) -> EM7_R {
224        EM7_R::new(((self.bits >> 7) & 1) != 0)
225    }
226    ///Bit 8 - Event Mask on line 8
227    #[inline(always)]
228    pub fn em8(&self) -> EM8_R {
229        EM8_R::new(((self.bits >> 8) & 1) != 0)
230    }
231    ///Bit 9 - Event Mask on line 9
232    #[inline(always)]
233    pub fn em9(&self) -> EM9_R {
234        EM9_R::new(((self.bits >> 9) & 1) != 0)
235    }
236    ///Bit 10 - Event Mask on line 10
237    #[inline(always)]
238    pub fn em10(&self) -> EM10_R {
239        EM10_R::new(((self.bits >> 10) & 1) != 0)
240    }
241    ///Bit 11 - Event Mask on line 11
242    #[inline(always)]
243    pub fn em11(&self) -> EM11_R {
244        EM11_R::new(((self.bits >> 11) & 1) != 0)
245    }
246    ///Bit 12 - Event Mask on line 12
247    #[inline(always)]
248    pub fn em12(&self) -> EM12_R {
249        EM12_R::new(((self.bits >> 12) & 1) != 0)
250    }
251    ///Bit 13 - Event Mask on line 13
252    #[inline(always)]
253    pub fn em13(&self) -> EM13_R {
254        EM13_R::new(((self.bits >> 13) & 1) != 0)
255    }
256    ///Bit 14 - Event Mask on line 14
257    #[inline(always)]
258    pub fn em14(&self) -> EM14_R {
259        EM14_R::new(((self.bits >> 14) & 1) != 0)
260    }
261    ///Bit 15 - Event Mask on line 15
262    #[inline(always)]
263    pub fn em15(&self) -> EM15_R {
264        EM15_R::new(((self.bits >> 15) & 1) != 0)
265    }
266    ///Bit 16 - Event Mask on line 16
267    #[inline(always)]
268    pub fn em16(&self) -> EM16_R {
269        EM16_R::new(((self.bits >> 16) & 1) != 0)
270    }
271    ///Bit 17 - Event Mask on line 17
272    #[inline(always)]
273    pub fn em17(&self) -> EM17_R {
274        EM17_R::new(((self.bits >> 17) & 1) != 0)
275    }
276    ///Bit 18 - Event Mask on line 18
277    #[inline(always)]
278    pub fn em18(&self) -> EM18_R {
279        EM18_R::new(((self.bits >> 18) & 1) != 0)
280    }
281    ///Bit 19 - Event Mask on line 19
282    #[inline(always)]
283    pub fn em19(&self) -> EM19_R {
284        EM19_R::new(((self.bits >> 19) & 1) != 0)
285    }
286    ///Bit 20 - Event Mask on line 20
287    #[inline(always)]
288    pub fn em20(&self) -> EM20_R {
289        EM20_R::new(((self.bits >> 20) & 1) != 0)
290    }
291    ///Bit 21 - Event Mask on line 21
292    #[inline(always)]
293    pub fn em21(&self) -> EM21_R {
294        EM21_R::new(((self.bits >> 21) & 1) != 0)
295    }
296    ///Bit 22 - Event Mask on line 22
297    #[inline(always)]
298    pub fn em22(&self) -> EM22_R {
299        EM22_R::new(((self.bits >> 22) & 1) != 0)
300    }
301    ///Bit 23 - Event Mask on line 23
302    #[inline(always)]
303    pub fn em23(&self) -> EM23_R {
304        EM23_R::new(((self.bits >> 23) & 1) != 0)
305    }
306    ///Bit 24 - Event Mask on line 24
307    #[inline(always)]
308    pub fn em24(&self) -> EM24_R {
309        EM24_R::new(((self.bits >> 24) & 1) != 0)
310    }
311    ///Bit 25 - Event Mask on line 25
312    #[inline(always)]
313    pub fn em25(&self) -> EM25_R {
314        EM25_R::new(((self.bits >> 25) & 1) != 0)
315    }
316    ///Bit 26 - Event Mask on line 26
317    #[inline(always)]
318    pub fn em26(&self) -> EM26_R {
319        EM26_R::new(((self.bits >> 26) & 1) != 0)
320    }
321    ///Bit 27 - Event Mask on line 27
322    #[inline(always)]
323    pub fn em27(&self) -> EM27_R {
324        EM27_R::new(((self.bits >> 27) & 1) != 0)
325    }
326    ///Bit 28 - Event Mask on line 28
327    #[inline(always)]
328    pub fn em28(&self) -> EM28_R {
329        EM28_R::new(((self.bits >> 28) & 1) != 0)
330    }
331    ///Bit 29 - Event Mask on line 29
332    #[inline(always)]
333    pub fn em29(&self) -> EM29_R {
334        EM29_R::new(((self.bits >> 29) & 1) != 0)
335    }
336    ///Bit 30 - Event Mask on line 30
337    #[inline(always)]
338    pub fn em30(&self) -> EM30_R {
339        EM30_R::new(((self.bits >> 30) & 1) != 0)
340    }
341    ///Bit 31 - Event Mask on line 31
342    #[inline(always)]
343    pub fn em31(&self) -> EM31_R {
344        EM31_R::new(((self.bits >> 31) & 1) != 0)
345    }
346}
347impl core::fmt::Debug for R {
348    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
349        f.debug_struct("EMR1")
350            .field("em0", &self.em0())
351            .field("em1", &self.em1())
352            .field("em2", &self.em2())
353            .field("em3", &self.em3())
354            .field("em4", &self.em4())
355            .field("em5", &self.em5())
356            .field("em6", &self.em6())
357            .field("em7", &self.em7())
358            .field("em8", &self.em8())
359            .field("em9", &self.em9())
360            .field("em10", &self.em10())
361            .field("em11", &self.em11())
362            .field("em12", &self.em12())
363            .field("em13", &self.em13())
364            .field("em14", &self.em14())
365            .field("em15", &self.em15())
366            .field("em16", &self.em16())
367            .field("em17", &self.em17())
368            .field("em18", &self.em18())
369            .field("em19", &self.em19())
370            .field("em20", &self.em20())
371            .field("em21", &self.em21())
372            .field("em22", &self.em22())
373            .field("em23", &self.em23())
374            .field("em24", &self.em24())
375            .field("em25", &self.em25())
376            .field("em26", &self.em26())
377            .field("em27", &self.em27())
378            .field("em28", &self.em28())
379            .field("em29", &self.em29())
380            .field("em30", &self.em30())
381            .field("em31", &self.em31())
382            .finish()
383    }
384}
385impl W {
386    ///Bit 0 - Event Mask on line 0
387    #[inline(always)]
388    pub fn em0(&mut self) -> EM0_W<EMR1rs> {
389        EM0_W::new(self, 0)
390    }
391    ///Bit 1 - Event Mask on line 1
392    #[inline(always)]
393    pub fn em1(&mut self) -> EM1_W<EMR1rs> {
394        EM1_W::new(self, 1)
395    }
396    ///Bit 2 - Event Mask on line 2
397    #[inline(always)]
398    pub fn em2(&mut self) -> EM2_W<EMR1rs> {
399        EM2_W::new(self, 2)
400    }
401    ///Bit 3 - Event Mask on line 3
402    #[inline(always)]
403    pub fn em3(&mut self) -> EM3_W<EMR1rs> {
404        EM3_W::new(self, 3)
405    }
406    ///Bit 4 - Event Mask on line 4
407    #[inline(always)]
408    pub fn em4(&mut self) -> EM4_W<EMR1rs> {
409        EM4_W::new(self, 4)
410    }
411    ///Bit 5 - Event Mask on line 5
412    #[inline(always)]
413    pub fn em5(&mut self) -> EM5_W<EMR1rs> {
414        EM5_W::new(self, 5)
415    }
416    ///Bit 6 - Event Mask on line 6
417    #[inline(always)]
418    pub fn em6(&mut self) -> EM6_W<EMR1rs> {
419        EM6_W::new(self, 6)
420    }
421    ///Bit 7 - Event Mask on line 7
422    #[inline(always)]
423    pub fn em7(&mut self) -> EM7_W<EMR1rs> {
424        EM7_W::new(self, 7)
425    }
426    ///Bit 8 - Event Mask on line 8
427    #[inline(always)]
428    pub fn em8(&mut self) -> EM8_W<EMR1rs> {
429        EM8_W::new(self, 8)
430    }
431    ///Bit 9 - Event Mask on line 9
432    #[inline(always)]
433    pub fn em9(&mut self) -> EM9_W<EMR1rs> {
434        EM9_W::new(self, 9)
435    }
436    ///Bit 10 - Event Mask on line 10
437    #[inline(always)]
438    pub fn em10(&mut self) -> EM10_W<EMR1rs> {
439        EM10_W::new(self, 10)
440    }
441    ///Bit 11 - Event Mask on line 11
442    #[inline(always)]
443    pub fn em11(&mut self) -> EM11_W<EMR1rs> {
444        EM11_W::new(self, 11)
445    }
446    ///Bit 12 - Event Mask on line 12
447    #[inline(always)]
448    pub fn em12(&mut self) -> EM12_W<EMR1rs> {
449        EM12_W::new(self, 12)
450    }
451    ///Bit 13 - Event Mask on line 13
452    #[inline(always)]
453    pub fn em13(&mut self) -> EM13_W<EMR1rs> {
454        EM13_W::new(self, 13)
455    }
456    ///Bit 14 - Event Mask on line 14
457    #[inline(always)]
458    pub fn em14(&mut self) -> EM14_W<EMR1rs> {
459        EM14_W::new(self, 14)
460    }
461    ///Bit 15 - Event Mask on line 15
462    #[inline(always)]
463    pub fn em15(&mut self) -> EM15_W<EMR1rs> {
464        EM15_W::new(self, 15)
465    }
466    ///Bit 16 - Event Mask on line 16
467    #[inline(always)]
468    pub fn em16(&mut self) -> EM16_W<EMR1rs> {
469        EM16_W::new(self, 16)
470    }
471    ///Bit 17 - Event Mask on line 17
472    #[inline(always)]
473    pub fn em17(&mut self) -> EM17_W<EMR1rs> {
474        EM17_W::new(self, 17)
475    }
476    ///Bit 18 - Event Mask on line 18
477    #[inline(always)]
478    pub fn em18(&mut self) -> EM18_W<EMR1rs> {
479        EM18_W::new(self, 18)
480    }
481    ///Bit 19 - Event Mask on line 19
482    #[inline(always)]
483    pub fn em19(&mut self) -> EM19_W<EMR1rs> {
484        EM19_W::new(self, 19)
485    }
486    ///Bit 20 - Event Mask on line 20
487    #[inline(always)]
488    pub fn em20(&mut self) -> EM20_W<EMR1rs> {
489        EM20_W::new(self, 20)
490    }
491    ///Bit 21 - Event Mask on line 21
492    #[inline(always)]
493    pub fn em21(&mut self) -> EM21_W<EMR1rs> {
494        EM21_W::new(self, 21)
495    }
496    ///Bit 22 - Event Mask on line 22
497    #[inline(always)]
498    pub fn em22(&mut self) -> EM22_W<EMR1rs> {
499        EM22_W::new(self, 22)
500    }
501    ///Bit 23 - Event Mask on line 23
502    #[inline(always)]
503    pub fn em23(&mut self) -> EM23_W<EMR1rs> {
504        EM23_W::new(self, 23)
505    }
506    ///Bit 24 - Event Mask on line 24
507    #[inline(always)]
508    pub fn em24(&mut self) -> EM24_W<EMR1rs> {
509        EM24_W::new(self, 24)
510    }
511    ///Bit 25 - Event Mask on line 25
512    #[inline(always)]
513    pub fn em25(&mut self) -> EM25_W<EMR1rs> {
514        EM25_W::new(self, 25)
515    }
516    ///Bit 26 - Event Mask on line 26
517    #[inline(always)]
518    pub fn em26(&mut self) -> EM26_W<EMR1rs> {
519        EM26_W::new(self, 26)
520    }
521    ///Bit 27 - Event Mask on line 27
522    #[inline(always)]
523    pub fn em27(&mut self) -> EM27_W<EMR1rs> {
524        EM27_W::new(self, 27)
525    }
526    ///Bit 28 - Event Mask on line 28
527    #[inline(always)]
528    pub fn em28(&mut self) -> EM28_W<EMR1rs> {
529        EM28_W::new(self, 28)
530    }
531    ///Bit 29 - Event Mask on line 29
532    #[inline(always)]
533    pub fn em29(&mut self) -> EM29_W<EMR1rs> {
534        EM29_W::new(self, 29)
535    }
536    ///Bit 30 - Event Mask on line 30
537    #[inline(always)]
538    pub fn em30(&mut self) -> EM30_W<EMR1rs> {
539        EM30_W::new(self, 30)
540    }
541    ///Bit 31 - Event Mask on line 31
542    #[inline(always)]
543    pub fn em31(&mut self) -> EM31_W<EMR1rs> {
544        EM31_W::new(self, 31)
545    }
546}
547/**Event mask register
548
549You can [`read`](crate::Reg::read) this register and get [`emr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
550
551See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#EXTI:EMR1)*/
552pub struct EMR1rs;
553impl crate::RegisterSpec for EMR1rs {
554    type Ux = u32;
555}
556///`read()` method returns [`emr1::R`](R) reader structure
557impl crate::Readable for EMR1rs {}
558///`write(|w| ..)` method takes [`emr1::W`](W) writer structure
559impl crate::Writable for EMR1rs {
560    type Safety = crate::Unsafe;
561}
562///`reset()` method sets EMR1 to value 0
563impl crate::Resettable for EMR1rs {}
stm32g4_staging/stm32g484/exti/emr1.rs

stm32g4_staging/stm32g484/exti/
emr1.rs
