stm32g4_staging/stm32g474/hrtim_master/
icr.rs

1///Register `ICR` writer
2pub type W = crate::W<ICRrs>;
3/**Master Compare %s Interrupt flag clear
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CMP1CW {
9    ///1: Clears associated flag in ISR register
10    Clear = 1,
11}
12impl From<CMP1CW> for bool {
13    #[inline(always)]
14    fn from(variant: CMP1CW) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `CMPC(1-4)` writer - Master Compare %s Interrupt flag clear
19pub type CMPC_W<'a, REG> = crate::BitWriter1C<'a, REG, CMP1CW>;
20impl<'a, REG> CMPC_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clears associated flag in ISR register
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(CMP1CW::Clear)
28    }
29}
30///Field `REPC` writer - Repetition Interrupt flag clear
31pub use CMPC_W as REPC_W;
32///Field `SYNCC` writer - Sync Input Interrupt flag clear
33pub use CMPC_W as SYNCC_W;
34///Field `UPDC` writer - Master update Interrupt flag clear
35pub use CMPC_W as UPDC_W;
36impl core::fmt::Debug for crate::generic::Reg<ICRrs> {
37    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
38        write!(f, "(not readable)")
39    }
40}
41impl W {
42    ///Master Compare (1-4) Interrupt flag clear
43    ///
44    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CMP1C` field.</div>
45    #[inline(always)]
46    pub fn cmpc(&mut self, n: u8) -> CMPC_W<ICRrs> {
47        #[allow(clippy::no_effect)] [(); 4][n as usize];
48        CMPC_W::new(self, n)
49    }
50    ///Bit 0 - Master Compare 1 Interrupt flag clear
51    #[inline(always)]
52    pub fn cmp1c(&mut self) -> CMPC_W<ICRrs> {
53        CMPC_W::new(self, 0)
54    }
55    ///Bit 1 - Master Compare 2 Interrupt flag clear
56    #[inline(always)]
57    pub fn cmp2c(&mut self) -> CMPC_W<ICRrs> {
58        CMPC_W::new(self, 1)
59    }
60    ///Bit 2 - Master Compare 3 Interrupt flag clear
61    #[inline(always)]
62    pub fn cmp3c(&mut self) -> CMPC_W<ICRrs> {
63        CMPC_W::new(self, 2)
64    }
65    ///Bit 3 - Master Compare 4 Interrupt flag clear
66    #[inline(always)]
67    pub fn cmp4c(&mut self) -> CMPC_W<ICRrs> {
68        CMPC_W::new(self, 3)
69    }
70    ///Bit 4 - Repetition Interrupt flag clear
71    #[inline(always)]
72    pub fn repc(&mut self) -> REPC_W<ICRrs> {
73        REPC_W::new(self, 4)
74    }
75    ///Bit 5 - Sync Input Interrupt flag clear
76    #[inline(always)]
77    pub fn syncc(&mut self) -> SYNCC_W<ICRrs> {
78        SYNCC_W::new(self, 5)
79    }
80    ///Bit 6 - Master update Interrupt flag clear
81    #[inline(always)]
82    pub fn updc(&mut self) -> UPDC_W<ICRrs> {
83        UPDC_W::new(self, 6)
84    }
85}
86/**Master Timer Interrupt Clear Register
87
88You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#HRTIM_Master:ICR)*/
91pub struct ICRrs;
92impl crate::RegisterSpec for ICRrs {
93    type Ux = u32;
94}
95///`write(|w| ..)` method takes [`icr::W`](W) writer structure
96impl crate::Writable for ICRrs {
97    type Safety = crate::Unsafe;
98    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x7f;
99}
100///`reset()` method sets ICR to value 0
101impl crate::Resettable for ICRrs {}
stm32g4_staging/stm32g474/hrtim_master/icr.rs

stm32g4_staging/stm32g474/hrtim_master/
icr.rs
