stm32g4_staging/stm32g474/comp/
ccsr.rs

1///Register `C%sCSR` reader
2pub type R = crate::R<CCSRrs>;
3///Register `C%sCSR` writer
4pub type W = crate::W<CCSRrs>;
5///Field `EN` reader - EN
6pub type EN_R = crate::BitReader;
7///Field `EN` writer - EN
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `INMSEL` reader - INMSEL
10pub type INMSEL_R = crate::FieldReader;
11///Field `INMSEL` writer - INMSEL
12pub type INMSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13///Field `INPSEL` reader - INPSEL
14pub type INPSEL_R = crate::BitReader;
15///Field `INPSEL` writer - INPSEL
16pub type INPSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `POL` reader - POL
18pub type POL_R = crate::BitReader;
19///Field `POL` writer - POL
20pub type POL_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `HYST` reader - HYST
22pub type HYST_R = crate::FieldReader;
23///Field `HYST` writer - HYST
24pub type HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25///Field `BLANKSEL` reader - BLANKSEL
26pub type BLANKSEL_R = crate::FieldReader;
27///Field `BLANKSEL` writer - BLANKSEL
28pub type BLANKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29///Field `BRGEN` reader - BRGEN
30pub type BRGEN_R = crate::BitReader;
31///Field `BRGEN` writer - BRGEN
32pub type BRGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `SCALEN` reader - SCALEN
34pub type SCALEN_R = crate::BitReader;
35///Field `SCALEN` writer - SCALEN
36pub type SCALEN_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `VALUE` reader - VALUE
38pub type VALUE_R = crate::BitReader;
39///Field `LOCK` reader - LOCK
40pub type LOCK_R = crate::BitReader;
41///Field `LOCK` writer - LOCK
42pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
43impl R {
44    ///Bit 0 - EN
45    #[inline(always)]
46    pub fn en(&self) -> EN_R {
47        EN_R::new((self.bits & 1) != 0)
48    }
49    ///Bits 4:6 - INMSEL
50    #[inline(always)]
51    pub fn inmsel(&self) -> INMSEL_R {
52        INMSEL_R::new(((self.bits >> 4) & 7) as u8)
53    }
54    ///Bit 8 - INPSEL
55    #[inline(always)]
56    pub fn inpsel(&self) -> INPSEL_R {
57        INPSEL_R::new(((self.bits >> 8) & 1) != 0)
58    }
59    ///Bit 15 - POL
60    #[inline(always)]
61    pub fn pol(&self) -> POL_R {
62        POL_R::new(((self.bits >> 15) & 1) != 0)
63    }
64    ///Bits 16:18 - HYST
65    #[inline(always)]
66    pub fn hyst(&self) -> HYST_R {
67        HYST_R::new(((self.bits >> 16) & 7) as u8)
68    }
69    ///Bits 19:21 - BLANKSEL
70    #[inline(always)]
71    pub fn blanksel(&self) -> BLANKSEL_R {
72        BLANKSEL_R::new(((self.bits >> 19) & 7) as u8)
73    }
74    ///Bit 22 - BRGEN
75    #[inline(always)]
76    pub fn brgen(&self) -> BRGEN_R {
77        BRGEN_R::new(((self.bits >> 22) & 1) != 0)
78    }
79    ///Bit 23 - SCALEN
80    #[inline(always)]
81    pub fn scalen(&self) -> SCALEN_R {
82        SCALEN_R::new(((self.bits >> 23) & 1) != 0)
83    }
84    ///Bit 30 - VALUE
85    #[inline(always)]
86    pub fn value(&self) -> VALUE_R {
87        VALUE_R::new(((self.bits >> 30) & 1) != 0)
88    }
89    ///Bit 31 - LOCK
90    #[inline(always)]
91    pub fn lock(&self) -> LOCK_R {
92        LOCK_R::new(((self.bits >> 31) & 1) != 0)
93    }
94}
95impl core::fmt::Debug for R {
96    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
97        f.debug_struct("CCSR")
98            .field("en", &self.en())
99            .field("inmsel", &self.inmsel())
100            .field("inpsel", &self.inpsel())
101            .field("pol", &self.pol())
102            .field("hyst", &self.hyst())
103            .field("blanksel", &self.blanksel())
104            .field("brgen", &self.brgen())
105            .field("scalen", &self.scalen())
106            .field("value", &self.value())
107            .field("lock", &self.lock())
108            .finish()
109    }
110}
111impl W {
112    ///Bit 0 - EN
113    #[inline(always)]
114    pub fn en(&mut self) -> EN_W<CCSRrs> {
115        EN_W::new(self, 0)
116    }
117    ///Bits 4:6 - INMSEL
118    #[inline(always)]
119    pub fn inmsel(&mut self) -> INMSEL_W<CCSRrs> {
120        INMSEL_W::new(self, 4)
121    }
122    ///Bit 8 - INPSEL
123    #[inline(always)]
124    pub fn inpsel(&mut self) -> INPSEL_W<CCSRrs> {
125        INPSEL_W::new(self, 8)
126    }
127    ///Bit 15 - POL
128    #[inline(always)]
129    pub fn pol(&mut self) -> POL_W<CCSRrs> {
130        POL_W::new(self, 15)
131    }
132    ///Bits 16:18 - HYST
133    #[inline(always)]
134    pub fn hyst(&mut self) -> HYST_W<CCSRrs> {
135        HYST_W::new(self, 16)
136    }
137    ///Bits 19:21 - BLANKSEL
138    #[inline(always)]
139    pub fn blanksel(&mut self) -> BLANKSEL_W<CCSRrs> {
140        BLANKSEL_W::new(self, 19)
141    }
142    ///Bit 22 - BRGEN
143    #[inline(always)]
144    pub fn brgen(&mut self) -> BRGEN_W<CCSRrs> {
145        BRGEN_W::new(self, 22)
146    }
147    ///Bit 23 - SCALEN
148    #[inline(always)]
149    pub fn scalen(&mut self) -> SCALEN_W<CCSRrs> {
150        SCALEN_W::new(self, 23)
151    }
152    ///Bit 31 - LOCK
153    #[inline(always)]
154    pub fn lock(&mut self) -> LOCK_W<CCSRrs> {
155        LOCK_W::new(self, 31)
156    }
157}
158/**Comparator control/status register
159
160You can [`read`](crate::Reg::read) this register and get [`ccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#COMP:C[1]CSR)*/
163pub struct CCSRrs;
164impl crate::RegisterSpec for CCSRrs {
165    type Ux = u32;
166}
167///`read()` method returns [`ccsr::R`](R) reader structure
168impl crate::Readable for CCSRrs {}
169///`write(|w| ..)` method takes [`ccsr::W`](W) writer structure
170impl crate::Writable for CCSRrs {
171    type Safety = crate::Unsafe;
172}
173///`reset()` method sets C%sCSR to value 0
174impl crate::Resettable for CCSRrs {}
stm32g4_staging/stm32g474/comp/ccsr.rs

stm32g4_staging/stm32g474/comp/
ccsr.rs
