stm32g4_staging/stm32g441/tim1/
ecr.rs

1///Register `ECR` reader
2pub type R = crate::R<ECRrs>;
3///Register `ECR` writer
4pub type W = crate::W<ECRrs>;
5///Field `IE` reader - Index Enable
6pub type IE_R = crate::BitReader;
7///Field `IE` writer - Index Enable
8pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `IDIR` reader - Index Direction
10pub type IDIR_R = crate::FieldReader;
11///Field `IDIR` writer - Index Direction
12pub type IDIR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `IBLK` reader - Index Blanking
14pub type IBLK_R = crate::FieldReader;
15///Field `IBLK` writer - Index Blanking
16pub type IBLK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17///Field `FIDX` reader - First Index
18pub type FIDX_R = crate::BitReader;
19///Field `FIDX` writer - First Index
20pub type FIDX_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `IPOS` reader - Index Positioning
22pub type IPOS_R = crate::FieldReader;
23///Field `IPOS` writer - Index Positioning
24pub type IPOS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25///Field `PW` reader - Pulse width
26pub type PW_R = crate::FieldReader;
27///Field `PW` writer - Pulse width
28pub type PW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29///Field `PWPRSC` reader - Pulse Width prescaler
30pub type PWPRSC_R = crate::FieldReader;
31///Field `PWPRSC` writer - Pulse Width prescaler
32pub type PWPRSC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33impl R {
34    ///Bit 0 - Index Enable
35    #[inline(always)]
36    pub fn ie(&self) -> IE_R {
37        IE_R::new((self.bits & 1) != 0)
38    }
39    ///Bits 1:2 - Index Direction
40    #[inline(always)]
41    pub fn idir(&self) -> IDIR_R {
42        IDIR_R::new(((self.bits >> 1) & 3) as u8)
43    }
44    ///Bits 3:4 - Index Blanking
45    #[inline(always)]
46    pub fn iblk(&self) -> IBLK_R {
47        IBLK_R::new(((self.bits >> 3) & 3) as u8)
48    }
49    ///Bit 5 - First Index
50    #[inline(always)]
51    pub fn fidx(&self) -> FIDX_R {
52        FIDX_R::new(((self.bits >> 5) & 1) != 0)
53    }
54    ///Bits 6:7 - Index Positioning
55    #[inline(always)]
56    pub fn ipos(&self) -> IPOS_R {
57        IPOS_R::new(((self.bits >> 6) & 3) as u8)
58    }
59    ///Bits 16:23 - Pulse width
60    #[inline(always)]
61    pub fn pw(&self) -> PW_R {
62        PW_R::new(((self.bits >> 16) & 0xff) as u8)
63    }
64    ///Bits 24:26 - Pulse Width prescaler
65    #[inline(always)]
66    pub fn pwprsc(&self) -> PWPRSC_R {
67        PWPRSC_R::new(((self.bits >> 24) & 7) as u8)
68    }
69}
70impl core::fmt::Debug for R {
71    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
72        f.debug_struct("ECR")
73            .field("ie", &self.ie())
74            .field("idir", &self.idir())
75            .field("iblk", &self.iblk())
76            .field("fidx", &self.fidx())
77            .field("ipos", &self.ipos())
78            .field("pw", &self.pw())
79            .field("pwprsc", &self.pwprsc())
80            .finish()
81    }
82}
83impl W {
84    ///Bit 0 - Index Enable
85    #[inline(always)]
86    pub fn ie(&mut self) -> IE_W<ECRrs> {
87        IE_W::new(self, 0)
88    }
89    ///Bits 1:2 - Index Direction
90    #[inline(always)]
91    pub fn idir(&mut self) -> IDIR_W<ECRrs> {
92        IDIR_W::new(self, 1)
93    }
94    ///Bits 3:4 - Index Blanking
95    #[inline(always)]
96    pub fn iblk(&mut self) -> IBLK_W<ECRrs> {
97        IBLK_W::new(self, 3)
98    }
99    ///Bit 5 - First Index
100    #[inline(always)]
101    pub fn fidx(&mut self) -> FIDX_W<ECRrs> {
102        FIDX_W::new(self, 5)
103    }
104    ///Bits 6:7 - Index Positioning
105    #[inline(always)]
106    pub fn ipos(&mut self) -> IPOS_W<ECRrs> {
107        IPOS_W::new(self, 6)
108    }
109    ///Bits 16:23 - Pulse width
110    #[inline(always)]
111    pub fn pw(&mut self) -> PW_W<ECRrs> {
112        PW_W::new(self, 16)
113    }
114    ///Bits 24:26 - Pulse Width prescaler
115    #[inline(always)]
116    pub fn pwprsc(&mut self) -> PWPRSC_W<ECRrs> {
117        PWPRSC_W::new(self, 24)
118    }
119}
120/**DMA control register
121
122You can [`read`](crate::Reg::read) this register and get [`ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#TIM1:ECR)*/
125pub struct ECRrs;
126impl crate::RegisterSpec for ECRrs {
127    type Ux = u32;
128}
129///`read()` method returns [`ecr::R`](R) reader structure
130impl crate::Readable for ECRrs {}
131///`write(|w| ..)` method takes [`ecr::W`](W) writer structure
132impl crate::Writable for ECRrs {
133    type Safety = crate::Unsafe;
134}
135///`reset()` method sets ECR to value 0
136impl crate::Resettable for ECRrs {}
stm32g4_staging/stm32g441/tim1/ecr.rs

stm32g4_staging/stm32g441/tim1/
ecr.rs
