stm32g4_staging/stm32g441/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    icscr: ICSCR,
7    cfgr: CFGR,
8    pllcfgr: PLLCFGR,
9    _reserved4: [u8; 0x08],
10    cier: CIER,
11    cifr: CIFR,
12    cicr: CICR,
13    _reserved7: [u8; 0x04],
14    ahb1rstr: AHB1RSTR,
15    ahb2rstr: AHB2RSTR,
16    ahb3rstr: AHB3RSTR,
17    _reserved10: [u8; 0x04],
18    apb1rstr1: APB1RSTR1,
19    apb1rstr2: APB1RSTR2,
20    apb2rstr: APB2RSTR,
21    _reserved13: [u8; 0x04],
22    ahb1enr: AHB1ENR,
23    ahb2enr: AHB2ENR,
24    ahb3enr: AHB3ENR,
25    _reserved16: [u8; 0x04],
26    apb1enr1: APB1ENR1,
27    apb1enr2: APB1ENR2,
28    apb2enr: APB2ENR,
29    _reserved19: [u8; 0x04],
30    ahb1smenr: AHB1SMENR,
31    ahb2smenr: AHB2SMENR,
32    ahb3smenr: AHB3SMENR,
33    _reserved22: [u8; 0x04],
34    apb1smenr1: APB1SMENR1,
35    apb1smenr2: APB1SMENR2,
36    apb2smenr: APB2SMENR,
37    _reserved25: [u8; 0x04],
38    ccipr: CCIPR,
39    _reserved26: [u8; 0x04],
40    bdcr: BDCR,
41    csr: CSR,
42    crrcr: CRRCR,
43    ccipr2: CCIPR2,
44}
45impl RegisterBlock {
46    ///0x00 - Clock control register
47    #[inline(always)]
48    pub const fn cr(&self) -> &CR {
49        &self.cr
50    }
51    ///0x04 - Internal clock sources calibration register
52    #[inline(always)]
53    pub const fn icscr(&self) -> &ICSCR {
54        &self.icscr
55    }
56    ///0x08 - Clock configuration register
57    #[inline(always)]
58    pub const fn cfgr(&self) -> &CFGR {
59        &self.cfgr
60    }
61    ///0x0c - PLL configuration register
62    #[inline(always)]
63    pub const fn pllcfgr(&self) -> &PLLCFGR {
64        &self.pllcfgr
65    }
66    ///0x18 - Clock interrupt enable register
67    #[inline(always)]
68    pub const fn cier(&self) -> &CIER {
69        &self.cier
70    }
71    ///0x1c - Clock interrupt flag register
72    #[inline(always)]
73    pub const fn cifr(&self) -> &CIFR {
74        &self.cifr
75    }
76    ///0x20 - Clock interrupt clear register
77    #[inline(always)]
78    pub const fn cicr(&self) -> &CICR {
79        &self.cicr
80    }
81    ///0x28 - AHB1 peripheral reset register
82    #[inline(always)]
83    pub const fn ahb1rstr(&self) -> &AHB1RSTR {
84        &self.ahb1rstr
85    }
86    ///0x2c - AHB2 peripheral reset register
87    #[inline(always)]
88    pub const fn ahb2rstr(&self) -> &AHB2RSTR {
89        &self.ahb2rstr
90    }
91    ///0x30 - AHB3 peripheral reset register
92    #[inline(always)]
93    pub const fn ahb3rstr(&self) -> &AHB3RSTR {
94        &self.ahb3rstr
95    }
96    ///0x38 - APB1 peripheral reset register 1
97    #[inline(always)]
98    pub const fn apb1rstr1(&self) -> &APB1RSTR1 {
99        &self.apb1rstr1
100    }
101    ///0x3c - APB1 peripheral reset register 2
102    #[inline(always)]
103    pub const fn apb1rstr2(&self) -> &APB1RSTR2 {
104        &self.apb1rstr2
105    }
106    ///0x40 - APB2 peripheral reset register
107    #[inline(always)]
108    pub const fn apb2rstr(&self) -> &APB2RSTR {
109        &self.apb2rstr
110    }
111    ///0x48 - AHB1 peripheral clock enable register
112    #[inline(always)]
113    pub const fn ahb1enr(&self) -> &AHB1ENR {
114        &self.ahb1enr
115    }
116    ///0x4c - AHB2 peripheral clock enable register
117    #[inline(always)]
118    pub const fn ahb2enr(&self) -> &AHB2ENR {
119        &self.ahb2enr
120    }
121    ///0x50 - AHB3 peripheral clock enable register
122    #[inline(always)]
123    pub const fn ahb3enr(&self) -> &AHB3ENR {
124        &self.ahb3enr
125    }
126    ///0x58 - APB1 peripheral clock enable register 1
127    #[inline(always)]
128    pub const fn apb1enr1(&self) -> &APB1ENR1 {
129        &self.apb1enr1
130    }
131    ///0x5c - APB1 peripheral clock enable register 2
132    #[inline(always)]
133    pub const fn apb1enr2(&self) -> &APB1ENR2 {
134        &self.apb1enr2
135    }
136    ///0x60 - APB2 peripheral clock enable register
137    #[inline(always)]
138    pub const fn apb2enr(&self) -> &APB2ENR {
139        &self.apb2enr
140    }
141    ///0x68 - AHB1 peripheral clocks enable in Sleep and Stop modes register
142    #[inline(always)]
143    pub const fn ahb1smenr(&self) -> &AHB1SMENR {
144        &self.ahb1smenr
145    }
146    ///0x6c - AHB2 peripheral clocks enable in Sleep and Stop modes register
147    #[inline(always)]
148    pub const fn ahb2smenr(&self) -> &AHB2SMENR {
149        &self.ahb2smenr
150    }
151    ///0x70 - AHB3 peripheral clocks enable in Sleep and Stop modes register
152    #[inline(always)]
153    pub const fn ahb3smenr(&self) -> &AHB3SMENR {
154        &self.ahb3smenr
155    }
156    ///0x78 - APB1 peripheral clocks enable in Sleep and Stop modes register 1
157    #[inline(always)]
158    pub const fn apb1smenr1(&self) -> &APB1SMENR1 {
159        &self.apb1smenr1
160    }
161    ///0x7c - APB1 peripheral clocks enable in Sleep and Stop modes register 2
162    #[inline(always)]
163    pub const fn apb1smenr2(&self) -> &APB1SMENR2 {
164        &self.apb1smenr2
165    }
166    ///0x80 - APB2 peripheral clocks enable in Sleep and Stop modes register
167    #[inline(always)]
168    pub const fn apb2smenr(&self) -> &APB2SMENR {
169        &self.apb2smenr
170    }
171    ///0x88 - Peripherals independent clock configuration register
172    #[inline(always)]
173    pub const fn ccipr(&self) -> &CCIPR {
174        &self.ccipr
175    }
176    ///0x90 - RTC domain control register
177    #[inline(always)]
178    pub const fn bdcr(&self) -> &BDCR {
179        &self.bdcr
180    }
181    ///0x94 - Control/status register
182    #[inline(always)]
183    pub const fn csr(&self) -> &CSR {
184        &self.csr
185    }
186    ///0x98 - Clock recovery RC register
187    #[inline(always)]
188    pub const fn crrcr(&self) -> &CRRCR {
189        &self.crrcr
190    }
191    ///0x9c - Peripherals independent clock configuration register
192    #[inline(always)]
193    pub const fn ccipr2(&self) -> &CCIPR2 {
194        &self.ccipr2
195    }
196}
197/**CR (rw) register accessor: Clock control register
198
199You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CR)
202
203For information about available fields see [`mod@cr`] module*/
204pub type CR = crate::Reg<cr::CRrs>;
205///Clock control register
206pub mod cr;
207/**ICSCR (rw) register accessor: Internal clock sources calibration register
208
209You can [`read`](crate::Reg::read) this register and get [`icscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:ICSCR)
212
213For information about available fields see [`mod@icscr`] module*/
214pub type ICSCR = crate::Reg<icscr::ICSCRrs>;
215///Internal clock sources calibration register
216pub mod icscr;
217/**CFGR (rw) register accessor: Clock configuration register
218
219You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CFGR)
222
223For information about available fields see [`mod@cfgr`] module*/
224pub type CFGR = crate::Reg<cfgr::CFGRrs>;
225///Clock configuration register
226pub mod cfgr;
227/**PLLCFGR (rw) register accessor: PLL configuration register
228
229You can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
230
231See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:PLLCFGR)
232
233For information about available fields see [`mod@pllcfgr`] module*/
234pub type PLLCFGR = crate::Reg<pllcfgr::PLLCFGRrs>;
235///PLL configuration register
236pub mod pllcfgr;
237/**CIER (rw) register accessor: Clock interrupt enable register
238
239You can [`read`](crate::Reg::read) this register and get [`cier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
240
241See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CIER)
242
243For information about available fields see [`mod@cier`] module*/
244pub type CIER = crate::Reg<cier::CIERrs>;
245///Clock interrupt enable register
246pub mod cier;
247/**CIFR (r) register accessor: Clock interrupt flag register
248
249You can [`read`](crate::Reg::read) this register and get [`cifr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
250
251See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CIFR)
252
253For information about available fields see [`mod@cifr`] module*/
254pub type CIFR = crate::Reg<cifr::CIFRrs>;
255///Clock interrupt flag register
256pub mod cifr;
257/**CICR (w) register accessor: Clock interrupt clear register
258
259You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cicr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
260
261See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CICR)
262
263For information about available fields see [`mod@cicr`] module*/
264pub type CICR = crate::Reg<cicr::CICRrs>;
265///Clock interrupt clear register
266pub mod cicr;
267/**AHB1RSTR (rw) register accessor: AHB1 peripheral reset register
268
269You can [`read`](crate::Reg::read) this register and get [`ahb1rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb1rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
270
271See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB1RSTR)
272
273For information about available fields see [`mod@ahb1rstr`] module*/
274pub type AHB1RSTR = crate::Reg<ahb1rstr::AHB1RSTRrs>;
275///AHB1 peripheral reset register
276pub mod ahb1rstr;
277/**AHB2RSTR (rw) register accessor: AHB2 peripheral reset register
278
279You can [`read`](crate::Reg::read) this register and get [`ahb2rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB2RSTR)
282
283For information about available fields see [`mod@ahb2rstr`] module*/
284pub type AHB2RSTR = crate::Reg<ahb2rstr::AHB2RSTRrs>;
285///AHB2 peripheral reset register
286pub mod ahb2rstr;
287/**AHB3RSTR (rw) register accessor: AHB3 peripheral reset register
288
289You can [`read`](crate::Reg::read) this register and get [`ahb3rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
290
291See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB3RSTR)
292
293For information about available fields see [`mod@ahb3rstr`] module*/
294pub type AHB3RSTR = crate::Reg<ahb3rstr::AHB3RSTRrs>;
295///AHB3 peripheral reset register
296pub mod ahb3rstr;
297/**APB1RSTR1 (rw) register accessor: APB1 peripheral reset register 1
298
299You can [`read`](crate::Reg::read) this register and get [`apb1rstr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
300
301See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1RSTR1)
302
303For information about available fields see [`mod@apb1rstr1`] module*/
304pub type APB1RSTR1 = crate::Reg<apb1rstr1::APB1RSTR1rs>;
305///APB1 peripheral reset register 1
306pub mod apb1rstr1;
307/**APB1RSTR2 (rw) register accessor: APB1 peripheral reset register 2
308
309You can [`read`](crate::Reg::read) this register and get [`apb1rstr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
310
311See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1RSTR2)
312
313For information about available fields see [`mod@apb1rstr2`] module*/
314pub type APB1RSTR2 = crate::Reg<apb1rstr2::APB1RSTR2rs>;
315///APB1 peripheral reset register 2
316pub mod apb1rstr2;
317/**APB2RSTR (rw) register accessor: APB2 peripheral reset register
318
319You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
320
321See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB2RSTR)
322
323For information about available fields see [`mod@apb2rstr`] module*/
324pub type APB2RSTR = crate::Reg<apb2rstr::APB2RSTRrs>;
325///APB2 peripheral reset register
326pub mod apb2rstr;
327/**AHB1ENR (rw) register accessor: AHB1 peripheral clock enable register
328
329You can [`read`](crate::Reg::read) this register and get [`ahb1enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb1enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
330
331See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB1ENR)
332
333For information about available fields see [`mod@ahb1enr`] module*/
334pub type AHB1ENR = crate::Reg<ahb1enr::AHB1ENRrs>;
335///AHB1 peripheral clock enable register
336pub mod ahb1enr;
337/**AHB2ENR (rw) register accessor: AHB2 peripheral clock enable register
338
339You can [`read`](crate::Reg::read) this register and get [`ahb2enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB2ENR)
342
343For information about available fields see [`mod@ahb2enr`] module*/
344pub type AHB2ENR = crate::Reg<ahb2enr::AHB2ENRrs>;
345///AHB2 peripheral clock enable register
346pub mod ahb2enr;
347/**AHB3ENR (rw) register accessor: AHB3 peripheral clock enable register
348
349You can [`read`](crate::Reg::read) this register and get [`ahb3enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
350
351See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB3ENR)
352
353For information about available fields see [`mod@ahb3enr`] module*/
354pub type AHB3ENR = crate::Reg<ahb3enr::AHB3ENRrs>;
355///AHB3 peripheral clock enable register
356pub mod ahb3enr;
357/**APB1ENR1 (rw) register accessor: APB1 peripheral clock enable register 1
358
359You can [`read`](crate::Reg::read) this register and get [`apb1enr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
360
361See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1ENR1)
362
363For information about available fields see [`mod@apb1enr1`] module*/
364pub type APB1ENR1 = crate::Reg<apb1enr1::APB1ENR1rs>;
365///APB1 peripheral clock enable register 1
366pub mod apb1enr1;
367/**APB1ENR2 (rw) register accessor: APB1 peripheral clock enable register 2
368
369You can [`read`](crate::Reg::read) this register and get [`apb1enr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
370
371See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1ENR2)
372
373For information about available fields see [`mod@apb1enr2`] module*/
374pub type APB1ENR2 = crate::Reg<apb1enr2::APB1ENR2rs>;
375///APB1 peripheral clock enable register 2
376pub mod apb1enr2;
377/**APB2ENR (rw) register accessor: APB2 peripheral clock enable register
378
379You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
380
381See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB2ENR)
382
383For information about available fields see [`mod@apb2enr`] module*/
384pub type APB2ENR = crate::Reg<apb2enr::APB2ENRrs>;
385///APB2 peripheral clock enable register
386pub mod apb2enr;
387/**AHB1SMENR (rw) register accessor: AHB1 peripheral clocks enable in Sleep and Stop modes register
388
389You can [`read`](crate::Reg::read) this register and get [`ahb1smenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb1smenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
390
391See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB1SMENR)
392
393For information about available fields see [`mod@ahb1smenr`] module*/
394pub type AHB1SMENR = crate::Reg<ahb1smenr::AHB1SMENRrs>;
395///AHB1 peripheral clocks enable in Sleep and Stop modes register
396pub mod ahb1smenr;
397/**AHB2SMENR (rw) register accessor: AHB2 peripheral clocks enable in Sleep and Stop modes register
398
399You can [`read`](crate::Reg::read) this register and get [`ahb2smenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2smenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
400
401See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB2SMENR)
402
403For information about available fields see [`mod@ahb2smenr`] module*/
404pub type AHB2SMENR = crate::Reg<ahb2smenr::AHB2SMENRrs>;
405///AHB2 peripheral clocks enable in Sleep and Stop modes register
406pub mod ahb2smenr;
407/**AHB3SMENR (rw) register accessor: AHB3 peripheral clocks enable in Sleep and Stop modes register
408
409You can [`read`](crate::Reg::read) this register and get [`ahb3smenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3smenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
410
411See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:AHB3SMENR)
412
413For information about available fields see [`mod@ahb3smenr`] module*/
414pub type AHB3SMENR = crate::Reg<ahb3smenr::AHB3SMENRrs>;
415///AHB3 peripheral clocks enable in Sleep and Stop modes register
416pub mod ahb3smenr;
417/**APB1SMENR1 (rw) register accessor: APB1 peripheral clocks enable in Sleep and Stop modes register 1
418
419You can [`read`](crate::Reg::read) this register and get [`apb1smenr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1smenr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
420
421See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1SMENR1)
422
423For information about available fields see [`mod@apb1smenr1`] module*/
424pub type APB1SMENR1 = crate::Reg<apb1smenr1::APB1SMENR1rs>;
425///APB1 peripheral clocks enable in Sleep and Stop modes register 1
426pub mod apb1smenr1;
427/**APB1SMENR2 (rw) register accessor: APB1 peripheral clocks enable in Sleep and Stop modes register 2
428
429You can [`read`](crate::Reg::read) this register and get [`apb1smenr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1smenr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
430
431See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB1SMENR2)
432
433For information about available fields see [`mod@apb1smenr2`] module*/
434pub type APB1SMENR2 = crate::Reg<apb1smenr2::APB1SMENR2rs>;
435///APB1 peripheral clocks enable in Sleep and Stop modes register 2
436pub mod apb1smenr2;
437/**APB2SMENR (rw) register accessor: APB2 peripheral clocks enable in Sleep and Stop modes register
438
439You can [`read`](crate::Reg::read) this register and get [`apb2smenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2smenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
440
441See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:APB2SMENR)
442
443For information about available fields see [`mod@apb2smenr`] module*/
444pub type APB2SMENR = crate::Reg<apb2smenr::APB2SMENRrs>;
445///APB2 peripheral clocks enable in Sleep and Stop modes register
446pub mod apb2smenr;
447/**CCIPR (rw) register accessor: Peripherals independent clock configuration register
448
449You can [`read`](crate::Reg::read) this register and get [`ccipr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
450
451See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CCIPR)
452
453For information about available fields see [`mod@ccipr`] module*/
454pub type CCIPR = crate::Reg<ccipr::CCIPRrs>;
455///Peripherals independent clock configuration register
456pub mod ccipr;
457/**BDCR (rw) register accessor: RTC domain control register
458
459You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
460
461See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:BDCR)
462
463For information about available fields see [`mod@bdcr`] module*/
464pub type BDCR = crate::Reg<bdcr::BDCRrs>;
465///RTC domain control register
466pub mod bdcr;
467/**CSR (rw) register accessor: Control/status register
468
469You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
470
471See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CSR)
472
473For information about available fields see [`mod@csr`] module*/
474pub type CSR = crate::Reg<csr::CSRrs>;
475///Control/status register
476pub mod csr;
477/**CRRCR (rw) register accessor: Clock recovery RC register
478
479You can [`read`](crate::Reg::read) this register and get [`crrcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crrcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
480
481See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CRRCR)
482
483For information about available fields see [`mod@crrcr`] module*/
484pub type CRRCR = crate::Reg<crrcr::CRRCRrs>;
485///Clock recovery RC register
486pub mod crrcr;
487/**CCIPR2 (rw) register accessor: Peripherals independent clock configuration register
488
489You can [`read`](crate::Reg::read) this register and get [`ccipr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
490
491See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#RCC:CCIPR2)
492
493For information about available fields see [`mod@ccipr2`] module*/
494pub type CCIPR2 = crate::Reg<ccipr2::CCIPR2rs>;
495///Peripherals independent clock configuration register
496pub mod ccipr2;
stm32g4_staging/stm32g441/rcc.rs

stm32g4_staging/stm32g441/
rcc.rs
