stm32g4_staging/stm32g441/i2c1/
timingr.rs

1///Register `TIMINGR` reader
2pub type R = crate::R<TIMINGRrs>;
3///Register `TIMINGR` writer
4pub type W = crate::W<TIMINGRrs>;
5///Field `SCLL` reader - SCL low period (master mode)
6pub type SCLL_R = crate::FieldReader;
7///Field `SCLL` writer - SCL low period (master mode)
8pub type SCLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
9///Field `SCLH` reader - SCL high period (master mode)
10pub type SCLH_R = crate::FieldReader;
11///Field `SCLH` writer - SCL high period (master mode)
12pub type SCLH_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
13///Field `SDADEL` reader - Data hold time
14pub type SDADEL_R = crate::FieldReader;
15///Field `SDADEL` writer - Data hold time
16pub type SDADEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
17///Field `SCLDEL` reader - Data setup time
18pub type SCLDEL_R = crate::FieldReader;
19///Field `SCLDEL` writer - Data setup time
20pub type SCLDEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
21///Field `PRESC` reader - Timing prescaler
22pub type PRESC_R = crate::FieldReader;
23///Field `PRESC` writer - Timing prescaler
24pub type PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
25impl R {
26    ///Bits 0:7 - SCL low period (master mode)
27    #[inline(always)]
28    pub fn scll(&self) -> SCLL_R {
29        SCLL_R::new((self.bits & 0xff) as u8)
30    }
31    ///Bits 8:15 - SCL high period (master mode)
32    #[inline(always)]
33    pub fn sclh(&self) -> SCLH_R {
34        SCLH_R::new(((self.bits >> 8) & 0xff) as u8)
35    }
36    ///Bits 16:19 - Data hold time
37    #[inline(always)]
38    pub fn sdadel(&self) -> SDADEL_R {
39        SDADEL_R::new(((self.bits >> 16) & 0x0f) as u8)
40    }
41    ///Bits 20:23 - Data setup time
42    #[inline(always)]
43    pub fn scldel(&self) -> SCLDEL_R {
44        SCLDEL_R::new(((self.bits >> 20) & 0x0f) as u8)
45    }
46    ///Bits 28:31 - Timing prescaler
47    #[inline(always)]
48    pub fn presc(&self) -> PRESC_R {
49        PRESC_R::new(((self.bits >> 28) & 0x0f) as u8)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("TIMINGR")
55            .field("scll", &self.scll())
56            .field("sclh", &self.sclh())
57            .field("sdadel", &self.sdadel())
58            .field("scldel", &self.scldel())
59            .field("presc", &self.presc())
60            .finish()
61    }
62}
63impl W {
64    ///Bits 0:7 - SCL low period (master mode)
65    #[inline(always)]
66    pub fn scll(&mut self) -> SCLL_W<TIMINGRrs> {
67        SCLL_W::new(self, 0)
68    }
69    ///Bits 8:15 - SCL high period (master mode)
70    #[inline(always)]
71    pub fn sclh(&mut self) -> SCLH_W<TIMINGRrs> {
72        SCLH_W::new(self, 8)
73    }
74    ///Bits 16:19 - Data hold time
75    #[inline(always)]
76    pub fn sdadel(&mut self) -> SDADEL_W<TIMINGRrs> {
77        SDADEL_W::new(self, 16)
78    }
79    ///Bits 20:23 - Data setup time
80    #[inline(always)]
81    pub fn scldel(&mut self) -> SCLDEL_W<TIMINGRrs> {
82        SCLDEL_W::new(self, 20)
83    }
84    ///Bits 28:31 - Timing prescaler
85    #[inline(always)]
86    pub fn presc(&mut self) -> PRESC_W<TIMINGRrs> {
87        PRESC_W::new(self, 28)
88    }
89}
90/**Timing register
91
92You can [`read`](crate::Reg::read) this register and get [`timingr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timingr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#I2C1:TIMINGR)*/
95pub struct TIMINGRrs;
96impl crate::RegisterSpec for TIMINGRrs {
97    type Ux = u32;
98}
99///`read()` method returns [`timingr::R`](R) reader structure
100impl crate::Readable for TIMINGRrs {}
101///`write(|w| ..)` method takes [`timingr::W`](W) writer structure
102impl crate::Writable for TIMINGRrs {
103    type Safety = crate::Unsafe;
104}
105///`reset()` method sets TIMINGR to value 0
106impl crate::Resettable for TIMINGRrs {}
stm32g4_staging/stm32g441/i2c1/timingr.rs

stm32g4_staging/stm32g441/i2c1/
timingr.rs
