stm32g4_staging/stm32g441/dac1/
dhr8rd.rs

1///Register `DHR8RD` reader
2pub type R = crate::R<DHR8RDrs>;
3///Register `DHR8RD` writer
4pub type W = crate::W<DHR8RDrs>;
5///Field `DACCDHR(1-2)` reader - DAC channel%s 8-bit right-aligned data
6pub type DACCDHR_R = crate::FieldReader;
7///Field `DACCDHR(1-2)` writer - DAC channel%s 8-bit right-aligned data
8pub type DACCDHR_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
9impl R {
10    ///DAC channel(1-2) 8-bit right-aligned data
11    ///
12    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DACC1DHR` field.</div>
13    #[inline(always)]
14    pub fn daccdhr(&self, n: u8) -> DACCDHR_R {
15        #[allow(clippy::no_effect)] [(); 2][n as usize];
16        DACCDHR_R::new(((self.bits >> (n * 8)) & 0xff) as u8)
17    }
18    ///Iterator for array of:
19    ///DAC channel(1-2) 8-bit right-aligned data
20    #[inline(always)]
21    pub fn daccdhr_iter(&self) -> impl Iterator<Item = DACCDHR_R> + '_ {
22        (0..2).map(move |n| DACCDHR_R::new(((self.bits >> (n * 8)) & 0xff) as u8))
23    }
24    ///Bits 0:7 - DAC channel1 8-bit right-aligned data
25    #[inline(always)]
26    pub fn dacc1dhr(&self) -> DACCDHR_R {
27        DACCDHR_R::new((self.bits & 0xff) as u8)
28    }
29    ///Bits 8:15 - DAC channel2 8-bit right-aligned data
30    #[inline(always)]
31    pub fn dacc2dhr(&self) -> DACCDHR_R {
32        DACCDHR_R::new(((self.bits >> 8) & 0xff) as u8)
33    }
34}
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("DHR8RD")
38            .field("dacc1dhr", &self.dacc1dhr())
39            .field("dacc2dhr", &self.dacc2dhr())
40            .finish()
41    }
42}
43impl W {
44    ///DAC channel(1-2) 8-bit right-aligned data
45    ///
46    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DACC1DHR` field.</div>
47    #[inline(always)]
48    pub fn daccdhr(&mut self, n: u8) -> DACCDHR_W<DHR8RDrs> {
49        #[allow(clippy::no_effect)] [(); 2][n as usize];
50        DACCDHR_W::new(self, n * 8)
51    }
52    ///Bits 0:7 - DAC channel1 8-bit right-aligned data
53    #[inline(always)]
54    pub fn dacc1dhr(&mut self) -> DACCDHR_W<DHR8RDrs> {
55        DACCDHR_W::new(self, 0)
56    }
57    ///Bits 8:15 - DAC channel2 8-bit right-aligned data
58    #[inline(always)]
59    pub fn dacc2dhr(&mut self) -> DACCDHR_W<DHR8RDrs> {
60        DACCDHR_W::new(self, 8)
61    }
62}
63/**DUAL DAC 8-bit right aligned data holding register
64
65You can [`read`](crate::Reg::read) this register and get [`dhr8rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
66
67See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#DAC1:DHR8RD)*/
68pub struct DHR8RDrs;
69impl crate::RegisterSpec for DHR8RDrs {
70    type Ux = u32;
71}
72///`read()` method returns [`dhr8rd::R`](R) reader structure
73impl crate::Readable for DHR8RDrs {}
74///`write(|w| ..)` method takes [`dhr8rd::W`](W) writer structure
75impl crate::Writable for DHR8RDrs {
76    type Safety = crate::Unsafe;
77}
78///`reset()` method sets DHR8RD to value 0
79impl crate::Resettable for DHR8RDrs {}
stm32g4_staging/stm32g441/dac1/dhr8rd.rs

stm32g4_staging/stm32g441/dac1/
dhr8rd.rs
