stm32g4_staging/stm32g431/
mod.rs

1/*!Peripheral access API for STM32G431 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{
16    CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU,
17};
18#[cfg(feature = "rt")]
19pub use cortex_m_rt::interrupt;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn WWDG();
23    fn PVD_PVM();
24    fn RTC_TAMP_CSS_LSE();
25    fn RTC_WKUP();
26    fn FLASH();
27    fn RCC();
28    fn EXTI0();
29    fn EXTI1();
30    fn EXTI2();
31    fn EXTI3();
32    fn EXTI4();
33    fn DMA1_CH1();
34    fn DMA1_CH2();
35    fn DMA1_CH3();
36    fn DMA1_CH4();
37    fn DMA1_CH5();
38    fn DMA1_CH6();
39    fn ADC1_2();
40    fn USB_HP();
41    fn USB_LP();
42    fn FDCAN1_IT0();
43    fn FDCAN1_IT1();
44    fn EXTI9_5();
45    fn TIM1_BRK_TIM15();
46    fn TIM1_UP_TIM16();
47    fn TIM1_TRG_COM();
48    fn TIM1_CC();
49    fn TIM2();
50    fn TIM3();
51    fn TIM4();
52    fn I2C1_EV();
53    fn I2C1_ER();
54    fn I2C2_EV();
55    fn I2C2_ER();
56    fn SPI1();
57    fn SPI2();
58    fn USART1();
59    fn USART2();
60    fn USART3();
61    fn EXTI15_10();
62    fn RTC_ALARM();
63    fn USBWAKE_UP();
64    fn TIM8_BRK();
65    fn TIM8_UP();
66    fn TIM8_TRG_COM();
67    fn TIM8_CC();
68    fn LPTIM1();
69    fn SPI3();
70    fn UART4();
71    fn TIM6_DACUNDER();
72    fn TIM7();
73    fn DMA2_CH1();
74    fn DMA2_CH2();
75    fn DMA2_CH3();
76    fn DMA2_CH4();
77    fn DMA2_CH5();
78    fn UCPD1();
79    fn COMP1_2_3();
80    fn COMP4_5_6();
81    fn COMP7();
82    fn CRS();
83    fn SAI();
84    fn TIM20_BRK();
85    fn TIM20_UP();
86    fn TIM20_TRG_COM();
87    fn TIM20_CC();
88    fn FPU();
89    fn AES();
90    fn RNG();
91    fn LPUART();
92    fn I2C3_EV();
93    fn I2C3_ER();
94    fn DMAMUX_OVR();
95    fn DMA2_CH6();
96    fn CORDIC();
97    fn FMAC();
98}
99#[doc(hidden)]
100#[repr(C)]
101pub union Vector {
102    _handler: unsafe extern "C" fn(),
103    _reserved: u32,
104}
105#[cfg(feature = "rt")]
106#[doc(hidden)]
107#[link_section = ".vector_table.interrupts"]
108#[no_mangle]
109pub static __INTERRUPTS: [Vector; 102] = [
110    Vector { _handler: WWDG },
111    Vector { _handler: PVD_PVM },
112    Vector {
113        _handler: RTC_TAMP_CSS_LSE,
114    },
115    Vector { _handler: RTC_WKUP },
116    Vector { _handler: FLASH },
117    Vector { _handler: RCC },
118    Vector { _handler: EXTI0 },
119    Vector { _handler: EXTI1 },
120    Vector { _handler: EXTI2 },
121    Vector { _handler: EXTI3 },
122    Vector { _handler: EXTI4 },
123    Vector { _handler: DMA1_CH1 },
124    Vector { _handler: DMA1_CH2 },
125    Vector { _handler: DMA1_CH3 },
126    Vector { _handler: DMA1_CH4 },
127    Vector { _handler: DMA1_CH5 },
128    Vector { _handler: DMA1_CH6 },
129    Vector { _reserved: 0 },
130    Vector { _handler: ADC1_2 },
131    Vector { _handler: USB_HP },
132    Vector { _handler: USB_LP },
133    Vector { _handler: FDCAN1_IT0 },
134    Vector { _handler: FDCAN1_IT1 },
135    Vector { _handler: EXTI9_5 },
136    Vector { _handler: TIM1_BRK_TIM15 },
137    Vector { _handler: TIM1_UP_TIM16 },
138    Vector { _handler: TIM1_TRG_COM },
139    Vector { _handler: TIM1_CC },
140    Vector { _handler: TIM2 },
141    Vector { _handler: TIM3 },
142    Vector { _handler: TIM4 },
143    Vector { _handler: I2C1_EV },
144    Vector { _handler: I2C1_ER },
145    Vector { _handler: I2C2_EV },
146    Vector { _handler: I2C2_ER },
147    Vector { _handler: SPI1 },
148    Vector { _handler: SPI2 },
149    Vector { _handler: USART1 },
150    Vector { _handler: USART2 },
151    Vector { _handler: USART3 },
152    Vector { _handler: EXTI15_10 },
153    Vector { _handler: RTC_ALARM },
154    Vector { _handler: USBWAKE_UP },
155    Vector { _handler: TIM8_BRK },
156    Vector { _handler: TIM8_UP },
157    Vector { _handler: TIM8_TRG_COM },
158    Vector { _handler: TIM8_CC },
159    Vector { _reserved: 0 },
160    Vector { _reserved: 0 },
161    Vector { _handler: LPTIM1 },
162    Vector { _reserved: 0 },
163    Vector { _handler: SPI3 },
164    Vector { _handler: UART4 },
165    Vector { _reserved: 0 },
166    Vector { _handler: TIM6_DACUNDER },
167    Vector { _handler: TIM7 },
168    Vector { _handler: DMA2_CH1 },
169    Vector { _handler: DMA2_CH2 },
170    Vector { _handler: DMA2_CH3 },
171    Vector { _handler: DMA2_CH4 },
172    Vector { _handler: DMA2_CH5 },
173    Vector { _reserved: 0 },
174    Vector { _reserved: 0 },
175    Vector { _handler: UCPD1 },
176    Vector { _handler: COMP1_2_3 },
177    Vector { _handler: COMP4_5_6 },
178    Vector { _handler: COMP7 },
179    Vector { _reserved: 0 },
180    Vector { _reserved: 0 },
181    Vector { _reserved: 0 },
182    Vector { _reserved: 0 },
183    Vector { _reserved: 0 },
184    Vector { _reserved: 0 },
185    Vector { _reserved: 0 },
186    Vector { _reserved: 0 },
187    Vector { _handler: CRS },
188    Vector { _handler: SAI },
189    Vector { _handler: TIM20_BRK },
190    Vector { _handler: TIM20_UP },
191    Vector { _handler: TIM20_TRG_COM },
192    Vector { _handler: TIM20_CC },
193    Vector { _handler: FPU },
194    Vector { _reserved: 0 },
195    Vector { _reserved: 0 },
196    Vector { _reserved: 0 },
197    Vector { _handler: AES },
198    Vector { _reserved: 0 },
199    Vector { _reserved: 0 },
200    Vector { _reserved: 0 },
201    Vector { _reserved: 0 },
202    Vector { _handler: RNG },
203    Vector { _handler: LPUART },
204    Vector { _handler: I2C3_EV },
205    Vector { _handler: I2C3_ER },
206    Vector { _handler: DMAMUX_OVR },
207    Vector { _reserved: 0 },
208    Vector { _reserved: 0 },
209    Vector { _handler: DMA2_CH6 },
210    Vector { _reserved: 0 },
211    Vector { _reserved: 0 },
212    Vector { _handler: CORDIC },
213    Vector { _handler: FMAC },
214];
215///Enumeration of all the interrupts.
216#[cfg_attr(feature = "defmt", derive(defmt::Format))]
217#[derive(Copy, Clone, Debug, PartialEq, Eq)]
218#[repr(u16)]
219pub enum Interrupt {
220    ///0 - Window Watchdog interrupt
221    WWDG = 0,
222    ///1 - PVD through EXTI line detection
223    PVD_PVM = 1,
224    ///2 - RTC_TAMP_CSS_LSE
225    RTC_TAMP_CSS_LSE = 2,
226    ///3 - RTC Wakeup timer
227    RTC_WKUP = 3,
228    ///4 - FLASH
229    FLASH = 4,
230    ///5 - RCC global interrupt
231    RCC = 5,
232    ///6 - EXTI Line0 interrupt
233    EXTI0 = 6,
234    ///7 - EXTI Line1 interrupt
235    EXTI1 = 7,
236    ///8 - EXTI Line2 interrupt
237    EXTI2 = 8,
238    ///9 - EXTI Line3 interrupt
239    EXTI3 = 9,
240    ///10 - EXTI Line4 interrupt
241    EXTI4 = 10,
242    ///11 - DMA1 channel 1 interrupt
243    DMA1_CH1 = 11,
244    ///12 - DMA1 channel 2 interrupt
245    DMA1_CH2 = 12,
246    ///13 - DMA1 channel 3 interrupt
247    DMA1_CH3 = 13,
248    ///14 - DMA1 channel 4 interrupt
249    DMA1_CH4 = 14,
250    ///15 - DMA1 channel 5 interrupt
251    DMA1_CH5 = 15,
252    ///16 - DMA1 channel 6 interrupt
253    DMA1_CH6 = 16,
254    ///18 - ADC1 and ADC2 global interrupt
255    ADC1_2 = 18,
256    ///19 - USB_HP
257    USB_HP = 19,
258    ///20 - USB_LP
259    USB_LP = 20,
260    ///21 - FDCAN1 interrupt 0
261    FDCAN1_IT0 = 21,
262    ///22 - FDCAN1 interrupt 1
263    FDCAN1_IT1 = 22,
264    ///23 - EXTI9_5
265    EXTI9_5 = 23,
266    ///24 - TIM1_BRK_TIM15
267    TIM1_BRK_TIM15 = 24,
268    ///25 - TIM1_UP_TIM16
269    TIM1_UP_TIM16 = 25,
270    ///26 - TIM1_TRG_COM/
271    TIM1_TRG_COM = 26,
272    ///27 - TIM1 capture compare interrupt
273    TIM1_CC = 27,
274    ///28 - TIM2
275    TIM2 = 28,
276    ///29 - TIM3
277    TIM3 = 29,
278    ///30 - TIM4
279    TIM4 = 30,
280    ///31 - I2C1_EV
281    I2C1_EV = 31,
282    ///32 - I2C1_ER
283    I2C1_ER = 32,
284    ///33 - I2C2_EV
285    I2C2_EV = 33,
286    ///34 - I2C2_ER
287    I2C2_ER = 34,
288    ///35 - SPI1
289    SPI1 = 35,
290    ///36 - SPI2
291    SPI2 = 36,
292    ///37 - USART1
293    USART1 = 37,
294    ///38 - USART2
295    USART2 = 38,
296    ///39 - USART3
297    USART3 = 39,
298    ///40 - EXTI15_10
299    EXTI15_10 = 40,
300    ///41 - RTC_ALARM
301    RTC_ALARM = 41,
302    ///42 - USBWakeUP
303    USBWAKE_UP = 42,
304    ///43 - TIM8_BRK
305    TIM8_BRK = 43,
306    ///44 - TIM8_UP
307    TIM8_UP = 44,
308    ///45 - TIM8_TRG_COM
309    TIM8_TRG_COM = 45,
310    ///46 - TIM8_CC
311    TIM8_CC = 46,
312    ///49 - LPTIM1
313    LPTIM1 = 49,
314    ///51 - SPI3
315    SPI3 = 51,
316    ///52 - UART4
317    UART4 = 52,
318    ///54 - TIM6_DACUNDER
319    TIM6_DACUNDER = 54,
320    ///55 - TIM7
321    TIM7 = 55,
322    ///56 - DMA2_CH1
323    DMA2_CH1 = 56,
324    ///57 - DMA2_CH2
325    DMA2_CH2 = 57,
326    ///58 - DMA2_CH3
327    DMA2_CH3 = 58,
328    ///59 - DMA2_CH4
329    DMA2_CH4 = 59,
330    ///60 - DMA2_CH5
331    DMA2_CH5 = 60,
332    ///63 - UCPD1
333    UCPD1 = 63,
334    ///64 - COMP1_2_3
335    COMP1_2_3 = 64,
336    ///65 - COMP4_5_6
337    COMP4_5_6 = 65,
338    ///66 - COMP7
339    COMP7 = 66,
340    ///75 - CRS
341    CRS = 75,
342    ///76 - SAI
343    SAI = 76,
344    ///77 - TIM20_BRK
345    TIM20_BRK = 77,
346    ///78 - TIM20_UP
347    TIM20_UP = 78,
348    ///79 - TIM20_TRG_COM
349    TIM20_TRG_COM = 79,
350    ///80 - TIM20_CC
351    TIM20_CC = 80,
352    ///81 - Floating point unit interrupt
353    FPU = 81,
354    ///85 - AES
355    AES = 85,
356    ///90 - RNG
357    RNG = 90,
358    ///91 - LPUART
359    LPUART = 91,
360    ///92 - I2C3_EV
361    I2C3_EV = 92,
362    ///93 - I2C3_ER
363    I2C3_ER = 93,
364    ///94 - DMAMUX_OVR
365    DMAMUX_OVR = 94,
366    ///97 - DMA2_CH6
367    DMA2_CH6 = 97,
368    ///100 - Cordic
369    CORDIC = 100,
370    ///101 - FMAC
371    FMAC = 101,
372}
373unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
374    #[inline(always)]
375    fn number(self) -> u16 {
376        self as u16
377    }
378}
379///Cyclic redundancy check calculation unit
380///
381///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#CRC)
382pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
383impl core::fmt::Debug for CRC {
384    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
385        f.debug_struct("CRC").finish()
386    }
387}
388///Cyclic redundancy check calculation unit
389pub mod crc;
390///WinWATCHDOG
391///
392///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#IWDG)
393pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
394impl core::fmt::Debug for IWDG {
395    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
396        f.debug_struct("IWDG").finish()
397    }
398}
399///WinWATCHDOG
400pub mod iwdg;
401///System window watchdog
402///
403///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#WWDG)
404pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
405impl core::fmt::Debug for WWDG {
406    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
407        f.debug_struct("WWDG").finish()
408    }
409}
410///System window watchdog
411pub mod wwdg;
412///Inter-integrated circuit
413///
414///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#I2C1)
415pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
416impl core::fmt::Debug for I2C1 {
417    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
418        f.debug_struct("I2C1").finish()
419    }
420}
421///Inter-integrated circuit
422pub mod i2c1;
423///Inter-integrated circuit
424///
425///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#I2C1)
426pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
427impl core::fmt::Debug for I2C2 {
428    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
429        f.debug_struct("I2C2").finish()
430    }
431}
432///Inter-integrated circuit
433pub use self::i2c1 as i2c2;
434///Inter-integrated circuit
435///
436///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#I2C1)
437pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_7800>;
438impl core::fmt::Debug for I2C3 {
439    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
440        f.debug_struct("I2C3").finish()
441    }
442}
443///Inter-integrated circuit
444pub use self::i2c1 as i2c3;
445///Flash
446///
447///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#FLASH)
448pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
449impl core::fmt::Debug for FLASH {
450    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
451        f.debug_struct("FLASH").finish()
452    }
453}
454///Flash
455pub mod flash;
456///Debug support
457///
458///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DBGMCU)
459pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
460impl core::fmt::Debug for DBGMCU {
461    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
462        f.debug_struct("DBGMCU").finish()
463    }
464}
465///Debug support
466pub mod dbgmcu;
467///Reset and clock control
468///
469///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#RCC)
470pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
471impl core::fmt::Debug for RCC {
472    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
473        f.debug_struct("RCC").finish()
474    }
475}
476///Reset and clock control
477pub mod rcc;
478///Power control
479///
480///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#PWR)
481pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
482impl core::fmt::Debug for PWR {
483    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
484        f.debug_struct("PWR").finish()
485    }
486}
487///Power control
488pub mod pwr;
489///Random number generator
490///
491///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#RNG)
492pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
493impl core::fmt::Debug for RNG {
494    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
495        f.debug_struct("RNG").finish()
496    }
497}
498///Random number generator
499pub mod rng;
500///Advanced encryption standard hardware accelerator
501///
502///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#AES)
503pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
504impl core::fmt::Debug for AES {
505    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
506        f.debug_struct("AES").finish()
507    }
508}
509///Advanced encryption standard hardware accelerator
510pub mod aes;
511///General-purpose I/Os
512///
513///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOA)
514pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
515impl core::fmt::Debug for GPIOA {
516    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
517        f.debug_struct("GPIOA").finish()
518    }
519}
520///General-purpose I/Os
521pub mod gpioa;
522///General-purpose I/Os
523///
524///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOB)
525pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
526impl core::fmt::Debug for GPIOB {
527    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528        f.debug_struct("GPIOB").finish()
529    }
530}
531///General-purpose I/Os
532pub mod gpiob;
533///General-purpose I/Os
534///
535///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC)
536pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
537impl core::fmt::Debug for GPIOC {
538    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
539        f.debug_struct("GPIOC").finish()
540    }
541}
542///General-purpose I/Os
543pub mod gpioc;
544///General-purpose I/Os
545///
546///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC)
547pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
548impl core::fmt::Debug for GPIOD {
549    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
550        f.debug_struct("GPIOD").finish()
551    }
552}
553///General-purpose I/Os
554pub use self::gpioc as gpiod;
555///General-purpose I/Os
556///
557///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC)
558pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
559impl core::fmt::Debug for GPIOE {
560    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
561        f.debug_struct("GPIOE").finish()
562    }
563}
564///General-purpose I/Os
565pub use self::gpioc as gpioe;
566///General-purpose I/Os
567///
568///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC)
569pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
570impl core::fmt::Debug for GPIOF {
571    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
572        f.debug_struct("GPIOF").finish()
573    }
574}
575///General-purpose I/Os
576pub use self::gpioc as gpiof;
577///General-purpose I/Os
578///
579///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC)
580pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
581impl core::fmt::Debug for GPIOG {
582    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
583        f.debug_struct("GPIOG").finish()
584    }
585}
586///General-purpose I/Os
587pub use self::gpioc as gpiog;
588///General purpose timers
589///
590///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM15)
591pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
592impl core::fmt::Debug for TIM15 {
593    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
594        f.debug_struct("TIM15").finish()
595    }
596}
597///General purpose timers
598pub mod tim15;
599///General purpose timers
600///
601///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM16)
602pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
603impl core::fmt::Debug for TIM16 {
604    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
605        f.debug_struct("TIM16").finish()
606    }
607}
608///General purpose timers
609pub mod tim16;
610///General purpose timers
611///
612///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM16)
613pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4001_4800>;
614impl core::fmt::Debug for TIM17 {
615    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
616        f.debug_struct("TIM17").finish()
617    }
618}
619///General purpose timers
620pub use self::tim16 as tim17;
621///Advanced-timers
622///
623///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM1)
624pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
625impl core::fmt::Debug for TIM1 {
626    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
627        f.debug_struct("TIM1").finish()
628    }
629}
630///Advanced-timers
631pub mod tim1;
632///Advanced-timers
633///
634///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM1)
635pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
636impl core::fmt::Debug for TIM8 {
637    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
638        f.debug_struct("TIM8").finish()
639    }
640}
641///Advanced-timers
642pub use self::tim1 as tim8;
643///Advanced-timers
644///
645///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM1)
646pub type TIM20 = crate::Periph<tim1::RegisterBlock, 0x4001_5000>;
647impl core::fmt::Debug for TIM20 {
648    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
649        f.debug_struct("TIM20").finish()
650    }
651}
652///Advanced-timers
653pub use self::tim1 as tim20;
654///Advanced-timers
655///
656///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM2)
657pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
658impl core::fmt::Debug for TIM2 {
659    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
660        f.debug_struct("TIM2").finish()
661    }
662}
663///Advanced-timers
664pub mod tim2;
665///Advanced-timers
666///
667///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM3)
668pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
669impl core::fmt::Debug for TIM3 {
670    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
671        f.debug_struct("TIM3").finish()
672    }
673}
674///Advanced-timers
675pub mod tim3;
676///Advanced-timers
677///
678///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM3)
679pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
680impl core::fmt::Debug for TIM4 {
681    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
682        f.debug_struct("TIM4").finish()
683    }
684}
685///Advanced-timers
686pub use self::tim3 as tim4;
687///Basic-timers
688///
689///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM6)
690pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
691impl core::fmt::Debug for TIM6 {
692    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
693        f.debug_struct("TIM6").finish()
694    }
695}
696///Basic-timers
697pub mod tim6;
698///Basic-timers
699///
700///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TIM6)
701pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
702impl core::fmt::Debug for TIM7 {
703    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
704        f.debug_struct("TIM7").finish()
705    }
706}
707///Basic-timers
708pub use self::tim6 as tim7;
709///Low power timer
710///
711///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#LPTIMER1)
712pub type LPTIMER1 = crate::Periph<lptimer1::RegisterBlock, 0x4000_7c00>;
713impl core::fmt::Debug for LPTIMER1 {
714    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
715        f.debug_struct("LPTIMER1").finish()
716    }
717}
718///Low power timer
719pub mod lptimer1;
720///Universal synchronous asynchronous receiver transmitter
721///
722///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#USART1)
723pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
724impl core::fmt::Debug for USART1 {
725    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
726        f.debug_struct("USART1").finish()
727    }
728}
729///Universal synchronous asynchronous receiver transmitter
730pub mod usart1;
731///Universal synchronous asynchronous receiver transmitter
732///
733///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#USART1)
734pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
735impl core::fmt::Debug for USART2 {
736    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
737        f.debug_struct("USART2").finish()
738    }
739}
740///Universal synchronous asynchronous receiver transmitter
741pub use self::usart1 as usart2;
742///Universal synchronous asynchronous receiver transmitter
743///
744///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#USART1)
745pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
746impl core::fmt::Debug for USART3 {
747    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
748        f.debug_struct("USART3").finish()
749    }
750}
751///Universal synchronous asynchronous receiver transmitter
752pub use self::usart1 as usart3;
753///Universal synchronous asynchronous receiver transmitter
754///
755///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#UART4)
756pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
757impl core::fmt::Debug for UART4 {
758    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
759        f.debug_struct("UART4").finish()
760    }
761}
762///Universal synchronous asynchronous receiver transmitter
763pub mod uart4;
764///Universal synchronous asynchronous receiver transmitter
765///
766///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#LPUART1)
767pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_8000>;
768impl core::fmt::Debug for LPUART1 {
769    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
770        f.debug_struct("LPUART1").finish()
771    }
772}
773///Universal synchronous asynchronous receiver transmitter
774pub mod lpuart1;
775///Serial peripheral interface/Inter-IC sound
776///
777///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#SPI1)
778pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
779impl core::fmt::Debug for SPI1 {
780    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
781        f.debug_struct("SPI1").finish()
782    }
783}
784///Serial peripheral interface/Inter-IC sound
785pub mod spi1;
786///Serial peripheral interface/Inter-IC sound
787///
788///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#SPI1)
789pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
790impl core::fmt::Debug for SPI3 {
791    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
792        f.debug_struct("SPI3").finish()
793    }
794}
795///Serial peripheral interface/Inter-IC sound
796pub use self::spi1 as spi3;
797///Serial peripheral interface/Inter-IC sound
798///
799///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#SPI1)
800pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
801impl core::fmt::Debug for SPI2 {
802    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
803        f.debug_struct("SPI2").finish()
804    }
805}
806///Serial peripheral interface/Inter-IC sound
807pub use self::spi1 as spi2;
808///External interrupt/event controller
809///
810///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#EXTI)
811pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
812impl core::fmt::Debug for EXTI {
813    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
814        f.debug_struct("EXTI").finish()
815    }
816}
817///External interrupt/event controller
818pub mod exti;
819///Real-time clock
820///
821///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#RTC)
822pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
823impl core::fmt::Debug for RTC {
824    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
825        f.debug_struct("RTC").finish()
826    }
827}
828///Real-time clock
829pub mod rtc;
830///DMA controller
831///
832///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DMA1)
833pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
834impl core::fmt::Debug for DMA1 {
835    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
836        f.debug_struct("DMA1").finish()
837    }
838}
839///DMA controller
840pub mod dma1;
841///DMA controller
842///
843///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DMA1)
844pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
845impl core::fmt::Debug for DMA2 {
846    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
847        f.debug_struct("DMA2").finish()
848    }
849}
850///DMA controller
851pub use self::dma1 as dma2;
852///DMAMUX
853///
854///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DMAMUX)
855pub type DMAMUX = crate::Periph<dmamux::RegisterBlock, 0x4002_0800>;
856impl core::fmt::Debug for DMAMUX {
857    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
858        f.debug_struct("DMAMUX").finish()
859    }
860}
861///DMAMUX
862pub mod dmamux;
863///System configuration controller
864///
865///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#SYSCFG)
866pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
867impl core::fmt::Debug for SYSCFG {
868    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
869        f.debug_struct("SYSCFG").finish()
870    }
871}
872///System configuration controller
873pub mod syscfg;
874///Voltage reference buffer
875///
876///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#VREFBUF)
877pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x4001_0030>;
878impl core::fmt::Debug for VREFBUF {
879    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
880        f.debug_struct("VREFBUF").finish()
881    }
882}
883///Voltage reference buffer
884pub mod vrefbuf;
885///Comparator control and status register
886///
887///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#COMP)
888pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0200>;
889impl core::fmt::Debug for COMP {
890    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
891        f.debug_struct("COMP").finish()
892    }
893}
894///Comparator control and status register
895pub mod comp;
896///Operational amplifiers
897///
898///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#OPAMP)
899pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4001_0300>;
900impl core::fmt::Debug for OPAMP {
901    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
902        f.debug_struct("OPAMP").finish()
903    }
904}
905///Operational amplifiers
906pub mod opamp;
907///Digital-to-analog converter
908///
909///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DAC1)
910pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x5000_0800>;
911impl core::fmt::Debug for DAC1 {
912    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
913        f.debug_struct("DAC1").finish()
914    }
915}
916///Digital-to-analog converter
917pub mod dac1;
918///Digital-to-analog converter
919///
920///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DAC1)
921pub type DAC2 = crate::Periph<dac1::RegisterBlock, 0x5000_0c00>;
922impl core::fmt::Debug for DAC2 {
923    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
924        f.debug_struct("DAC2").finish()
925    }
926}
927///Digital-to-analog converter
928pub use self::dac1 as dac2;
929///Digital-to-analog converter
930///
931///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DAC1)
932pub type DAC3 = crate::Periph<dac1::RegisterBlock, 0x5000_1000>;
933impl core::fmt::Debug for DAC3 {
934    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
935        f.debug_struct("DAC3").finish()
936    }
937}
938///Digital-to-analog converter
939pub use self::dac1 as dac3;
940///Digital-to-analog converter
941///
942///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#DAC1)
943pub type DAC4 = crate::Periph<dac1::RegisterBlock, 0x5000_1400>;
944impl core::fmt::Debug for DAC4 {
945    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
946        f.debug_struct("DAC4").finish()
947    }
948}
949///Digital-to-analog converter
950pub use self::dac1 as dac4;
951///Analog-to-Digital Converter
952///
953///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#ADC1)
954pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5000_0000>;
955impl core::fmt::Debug for ADC1 {
956    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
957        f.debug_struct("ADC1").finish()
958    }
959}
960///Analog-to-Digital Converter
961pub mod adc1;
962///Analog-to-Digital Converter
963///
964///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#ADC1)
965pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5000_0100>;
966impl core::fmt::Debug for ADC2 {
967    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
968        f.debug_struct("ADC2").finish()
969    }
970}
971///Analog-to-Digital Converter
972pub use self::adc1 as adc2;
973///Analog-to-Digital Converter
974///
975///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#ADC12_Common)
976pub type ADC12_COMMON = crate::Periph<adc12_common::RegisterBlock, 0x5000_0300>;
977impl core::fmt::Debug for ADC12_COMMON {
978    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
979        f.debug_struct("ADC12_COMMON").finish()
980    }
981}
982///Analog-to-Digital Converter
983pub mod adc12_common;
984///Analog-to-Digital Converter
985///
986///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#ADC12_Common)
987pub type ADC345_COMMON = crate::Periph<adc12_common::RegisterBlock, 0x5000_0700>;
988impl core::fmt::Debug for ADC345_COMMON {
989    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
990        f.debug_struct("ADC345_COMMON").finish()
991    }
992}
993///Analog-to-Digital Converter
994pub use self::adc12_common as adc345_common;
995///Filter Math Accelerator
996///
997///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#FMAC)
998pub type FMAC = crate::Periph<fmac::RegisterBlock, 0x4002_1400>;
999impl core::fmt::Debug for FMAC {
1000    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1001        f.debug_struct("FMAC").finish()
1002    }
1003}
1004///Filter Math Accelerator
1005pub mod fmac;
1006///CORDIC Co-processor
1007///
1008///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#CORDIC)
1009pub type CORDIC = crate::Periph<cordic::RegisterBlock, 0x4002_0c00>;
1010impl core::fmt::Debug for CORDIC {
1011    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1012        f.debug_struct("CORDIC").finish()
1013    }
1014}
1015///CORDIC Co-processor
1016pub mod cordic;
1017///Serial audio interface
1018///
1019///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#SAI)
1020pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5400>;
1021impl core::fmt::Debug for SAI {
1022    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1023        f.debug_struct("SAI").finish()
1024    }
1025}
1026///Serial audio interface
1027pub mod sai;
1028///Tamper and backup registers
1029///
1030///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#TAMP)
1031pub type TAMP = crate::Periph<tamp::RegisterBlock, 0x4000_2400>;
1032impl core::fmt::Debug for TAMP {
1033    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1034        f.debug_struct("TAMP").finish()
1035    }
1036}
1037///Tamper and backup registers
1038pub mod tamp;
1039///FDCAN
1040///
1041///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#FDCAN)
1042pub type FDCAN = crate::Periph<fdcan::RegisterBlock, 0x4000_a400>;
1043impl core::fmt::Debug for FDCAN {
1044    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1045        f.debug_struct("FDCAN").finish()
1046    }
1047}
1048///FDCAN
1049pub mod fdcan;
1050///FDCAN
1051///
1052///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#FDCAN)
1053pub type FDCAN1 = crate::Periph<fdcan::RegisterBlock, 0x4000_6400>;
1054impl core::fmt::Debug for FDCAN1 {
1055    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1056        f.debug_struct("FDCAN1").finish()
1057    }
1058}
1059///FDCAN
1060pub use self::fdcan as fdcan1;
1061///UCPD1
1062///
1063///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#UCPD1)
1064pub type UCPD1 = crate::Periph<ucpd1::RegisterBlock, 0x4000_a000>;
1065impl core::fmt::Debug for UCPD1 {
1066    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1067        f.debug_struct("UCPD1").finish()
1068    }
1069}
1070///UCPD1
1071pub mod ucpd1;
1072///USB_FS_device
1073///
1074///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#USB)
1075pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
1076impl core::fmt::Debug for USB {
1077    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1078        f.debug_struct("USB").finish()
1079    }
1080}
1081///USB_FS_device
1082pub mod usb;
1083///CRS
1084///
1085///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#CRS)
1086pub type CRS = crate::Periph<crs::RegisterBlock, 0x4000_2000>;
1087impl core::fmt::Debug for CRS {
1088    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1089        f.debug_struct("CRS").finish()
1090    }
1091}
1092///CRS
1093pub mod crs;
1094#[no_mangle]
1095static mut DEVICE_PERIPHERALS: bool = false;
1096/// All the peripherals.
1097#[allow(non_snake_case)]
1098pub struct Peripherals {
1099    ///CRC
1100    pub CRC: CRC,
1101    ///IWDG
1102    pub IWDG: IWDG,
1103    ///WWDG
1104    pub WWDG: WWDG,
1105    ///I2C1
1106    pub I2C1: I2C1,
1107    ///I2C2
1108    pub I2C2: I2C2,
1109    ///I2C3
1110    pub I2C3: I2C3,
1111    ///FLASH
1112    pub FLASH: FLASH,
1113    ///DBGMCU
1114    pub DBGMCU: DBGMCU,
1115    ///RCC
1116    pub RCC: RCC,
1117    ///PWR
1118    pub PWR: PWR,
1119    ///RNG
1120    pub RNG: RNG,
1121    ///AES
1122    pub AES: AES,
1123    ///GPIOA
1124    pub GPIOA: GPIOA,
1125    ///GPIOB
1126    pub GPIOB: GPIOB,
1127    ///GPIOC
1128    pub GPIOC: GPIOC,
1129    ///GPIOD
1130    pub GPIOD: GPIOD,
1131    ///GPIOE
1132    pub GPIOE: GPIOE,
1133    ///GPIOF
1134    pub GPIOF: GPIOF,
1135    ///GPIOG
1136    pub GPIOG: GPIOG,
1137    ///TIM15
1138    pub TIM15: TIM15,
1139    ///TIM16
1140    pub TIM16: TIM16,
1141    ///TIM17
1142    pub TIM17: TIM17,
1143    ///TIM1
1144    pub TIM1: TIM1,
1145    ///TIM8
1146    pub TIM8: TIM8,
1147    ///TIM20
1148    pub TIM20: TIM20,
1149    ///TIM2
1150    pub TIM2: TIM2,
1151    ///TIM3
1152    pub TIM3: TIM3,
1153    ///TIM4
1154    pub TIM4: TIM4,
1155    ///TIM6
1156    pub TIM6: TIM6,
1157    ///TIM7
1158    pub TIM7: TIM7,
1159    ///LPTIMER1
1160    pub LPTIMER1: LPTIMER1,
1161    ///USART1
1162    pub USART1: USART1,
1163    ///USART2
1164    pub USART2: USART2,
1165    ///USART3
1166    pub USART3: USART3,
1167    ///UART4
1168    pub UART4: UART4,
1169    ///LPUART1
1170    pub LPUART1: LPUART1,
1171    ///SPI1
1172    pub SPI1: SPI1,
1173    ///SPI3
1174    pub SPI3: SPI3,
1175    ///SPI2
1176    pub SPI2: SPI2,
1177    ///EXTI
1178    pub EXTI: EXTI,
1179    ///RTC
1180    pub RTC: RTC,
1181    ///DMA1
1182    pub DMA1: DMA1,
1183    ///DMA2
1184    pub DMA2: DMA2,
1185    ///DMAMUX
1186    pub DMAMUX: DMAMUX,
1187    ///SYSCFG
1188    pub SYSCFG: SYSCFG,
1189    ///VREFBUF
1190    pub VREFBUF: VREFBUF,
1191    ///COMP
1192    pub COMP: COMP,
1193    ///OPAMP
1194    pub OPAMP: OPAMP,
1195    ///DAC1
1196    pub DAC1: DAC1,
1197    ///DAC2
1198    pub DAC2: DAC2,
1199    ///DAC3
1200    pub DAC3: DAC3,
1201    ///DAC4
1202    pub DAC4: DAC4,
1203    ///ADC1
1204    pub ADC1: ADC1,
1205    ///ADC2
1206    pub ADC2: ADC2,
1207    ///ADC12_Common
1208    pub ADC12_COMMON: ADC12_COMMON,
1209    ///ADC345_Common
1210    pub ADC345_COMMON: ADC345_COMMON,
1211    ///FMAC
1212    pub FMAC: FMAC,
1213    ///CORDIC
1214    pub CORDIC: CORDIC,
1215    ///SAI
1216    pub SAI: SAI,
1217    ///TAMP
1218    pub TAMP: TAMP,
1219    ///FDCAN
1220    pub FDCAN: FDCAN,
1221    ///FDCAN1
1222    pub FDCAN1: FDCAN1,
1223    ///UCPD1
1224    pub UCPD1: UCPD1,
1225    ///USB
1226    pub USB: USB,
1227    ///CRS
1228    pub CRS: CRS,
1229}
1230impl Peripherals {
1231    /// Returns all the peripherals *once*.
1232    #[cfg(feature = "critical-section")]
1233    #[inline]
1234    pub fn take() -> Option<Self> {
1235        critical_section::with(|_| {
1236            if unsafe { DEVICE_PERIPHERALS } {
1237                return None;
1238            }
1239            Some(unsafe { Peripherals::steal() })
1240        })
1241    }
1242    /// Unchecked version of `Peripherals::take`.
1243    ///
1244    /// # Safety
1245    ///
1246    /// Each of the returned peripherals must be used at most once.
1247    #[inline]
1248    pub unsafe fn steal() -> Self {
1249        DEVICE_PERIPHERALS = true;
1250        Peripherals {
1251            CRC: CRC::steal(),
1252            IWDG: IWDG::steal(),
1253            WWDG: WWDG::steal(),
1254            I2C1: I2C1::steal(),
1255            I2C2: I2C2::steal(),
1256            I2C3: I2C3::steal(),
1257            FLASH: FLASH::steal(),
1258            DBGMCU: DBGMCU::steal(),
1259            RCC: RCC::steal(),
1260            PWR: PWR::steal(),
1261            RNG: RNG::steal(),
1262            AES: AES::steal(),
1263            GPIOA: GPIOA::steal(),
1264            GPIOB: GPIOB::steal(),
1265            GPIOC: GPIOC::steal(),
1266            GPIOD: GPIOD::steal(),
1267            GPIOE: GPIOE::steal(),
1268            GPIOF: GPIOF::steal(),
1269            GPIOG: GPIOG::steal(),
1270            TIM15: TIM15::steal(),
1271            TIM16: TIM16::steal(),
1272            TIM17: TIM17::steal(),
1273            TIM1: TIM1::steal(),
1274            TIM8: TIM8::steal(),
1275            TIM20: TIM20::steal(),
1276            TIM2: TIM2::steal(),
1277            TIM3: TIM3::steal(),
1278            TIM4: TIM4::steal(),
1279            TIM6: TIM6::steal(),
1280            TIM7: TIM7::steal(),
1281            LPTIMER1: LPTIMER1::steal(),
1282            USART1: USART1::steal(),
1283            USART2: USART2::steal(),
1284            USART3: USART3::steal(),
1285            UART4: UART4::steal(),
1286            LPUART1: LPUART1::steal(),
1287            SPI1: SPI1::steal(),
1288            SPI3: SPI3::steal(),
1289            SPI2: SPI2::steal(),
1290            EXTI: EXTI::steal(),
1291            RTC: RTC::steal(),
1292            DMA1: DMA1::steal(),
1293            DMA2: DMA2::steal(),
1294            DMAMUX: DMAMUX::steal(),
1295            SYSCFG: SYSCFG::steal(),
1296            VREFBUF: VREFBUF::steal(),
1297            COMP: COMP::steal(),
1298            OPAMP: OPAMP::steal(),
1299            DAC1: DAC1::steal(),
1300            DAC2: DAC2::steal(),
1301            DAC3: DAC3::steal(),
1302            DAC4: DAC4::steal(),
1303            ADC1: ADC1::steal(),
1304            ADC2: ADC2::steal(),
1305            ADC12_COMMON: ADC12_COMMON::steal(),
1306            ADC345_COMMON: ADC345_COMMON::steal(),
1307            FMAC: FMAC::steal(),
1308            CORDIC: CORDIC::steal(),
1309            SAI: SAI::steal(),
1310            TAMP: TAMP::steal(),
1311            FDCAN: FDCAN::steal(),
1312            FDCAN1: FDCAN1::steal(),
1313            UCPD1: UCPD1::steal(),
1314            USB: USB::steal(),
1315            CRS: CRS::steal(),
1316        }
1317    }
1318}
stm32g4_staging/stm32g431/mod.rs

stm32g4_staging/stm32g431/
mod.rs
