stm32g4_staging/stm32g441/syscfg/
cfgr1.rs

1///Register `CFGR1` reader
2pub type R = crate::R<CFGR1rs>;
3///Register `CFGR1` writer
4pub type W = crate::W<CFGR1rs>;
5///Field `BOOSTEN` reader - BOOSTEN
6pub type BOOSTEN_R = crate::BitReader;
7///Field `BOOSTEN` writer - BOOSTEN
8pub type BOOSTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `ANASWVDD` reader - GPIO analog switch control voltage selection
10pub type ANASWVDD_R = crate::BitReader;
11///Field `ANASWVDD` writer - GPIO analog switch control voltage selection
12pub type ANASWVDD_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `I2C_PB6_FMP` reader - FM+ drive capability on PB6
14pub type I2C_PB6_FMP_R = crate::BitReader;
15///Field `I2C_PB6_FMP` writer - FM+ drive capability on PB6
16pub type I2C_PB6_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `I2C_PB7_FMP` reader - FM+ drive capability on PB6
18pub type I2C_PB7_FMP_R = crate::BitReader;
19///Field `I2C_PB7_FMP` writer - FM+ drive capability on PB6
20pub type I2C_PB7_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `I2C_PB8_FMP` reader - FM+ drive capability on PB6
22pub type I2C_PB8_FMP_R = crate::BitReader;
23///Field `I2C_PB8_FMP` writer - FM+ drive capability on PB6
24pub type I2C_PB8_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `I2C_PB9_FMP` reader - FM+ drive capability on PB6
26pub type I2C_PB9_FMP_R = crate::BitReader;
27///Field `I2C_PB9_FMP` writer - FM+ drive capability on PB6
28pub type I2C_PB9_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `I2C1_FMP` reader - I2C1 FM+ drive capability enable
30pub type I2C1_FMP_R = crate::BitReader;
31///Field `I2C1_FMP` writer - I2C1 FM+ drive capability enable
32pub type I2C1_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `I2C2_FMP` reader - I2C1 FM+ drive capability enable
34pub type I2C2_FMP_R = crate::BitReader;
35///Field `I2C2_FMP` writer - I2C1 FM+ drive capability enable
36pub type I2C2_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `I2C3_FMP` reader - I2C1 FM+ drive capability enable
38pub type I2C3_FMP_R = crate::BitReader;
39///Field `I2C3_FMP` writer - I2C1 FM+ drive capability enable
40pub type I2C3_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `I2C4_FMP` reader - I2C1 FM+ drive capability enable
42pub type I2C4_FMP_R = crate::BitReader;
43///Field `I2C4_FMP` writer - I2C1 FM+ drive capability enable
44pub type I2C4_FMP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `FPU_IE` reader - FPU Interrupts Enable
46pub type FPU_IE_R = crate::FieldReader;
47///Field `FPU_IE` writer - FPU Interrupts Enable
48pub type FPU_IE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
49impl R {
50    ///Bit 8 - BOOSTEN
51    #[inline(always)]
52    pub fn boosten(&self) -> BOOSTEN_R {
53        BOOSTEN_R::new(((self.bits >> 8) & 1) != 0)
54    }
55    ///Bit 9 - GPIO analog switch control voltage selection
56    #[inline(always)]
57    pub fn anaswvdd(&self) -> ANASWVDD_R {
58        ANASWVDD_R::new(((self.bits >> 9) & 1) != 0)
59    }
60    ///Bit 16 - FM+ drive capability on PB6
61    #[inline(always)]
62    pub fn i2c_pb6_fmp(&self) -> I2C_PB6_FMP_R {
63        I2C_PB6_FMP_R::new(((self.bits >> 16) & 1) != 0)
64    }
65    ///Bit 17 - FM+ drive capability on PB6
66    #[inline(always)]
67    pub fn i2c_pb7_fmp(&self) -> I2C_PB7_FMP_R {
68        I2C_PB7_FMP_R::new(((self.bits >> 17) & 1) != 0)
69    }
70    ///Bit 18 - FM+ drive capability on PB6
71    #[inline(always)]
72    pub fn i2c_pb8_fmp(&self) -> I2C_PB8_FMP_R {
73        I2C_PB8_FMP_R::new(((self.bits >> 18) & 1) != 0)
74    }
75    ///Bit 19 - FM+ drive capability on PB6
76    #[inline(always)]
77    pub fn i2c_pb9_fmp(&self) -> I2C_PB9_FMP_R {
78        I2C_PB9_FMP_R::new(((self.bits >> 19) & 1) != 0)
79    }
80    ///Bit 20 - I2C1 FM+ drive capability enable
81    #[inline(always)]
82    pub fn i2c1_fmp(&self) -> I2C1_FMP_R {
83        I2C1_FMP_R::new(((self.bits >> 20) & 1) != 0)
84    }
85    ///Bit 21 - I2C1 FM+ drive capability enable
86    #[inline(always)]
87    pub fn i2c2_fmp(&self) -> I2C2_FMP_R {
88        I2C2_FMP_R::new(((self.bits >> 21) & 1) != 0)
89    }
90    ///Bit 22 - I2C1 FM+ drive capability enable
91    #[inline(always)]
92    pub fn i2c3_fmp(&self) -> I2C3_FMP_R {
93        I2C3_FMP_R::new(((self.bits >> 22) & 1) != 0)
94    }
95    ///Bit 23 - I2C1 FM+ drive capability enable
96    #[inline(always)]
97    pub fn i2c4_fmp(&self) -> I2C4_FMP_R {
98        I2C4_FMP_R::new(((self.bits >> 23) & 1) != 0)
99    }
100    ///Bits 26:31 - FPU Interrupts Enable
101    #[inline(always)]
102    pub fn fpu_ie(&self) -> FPU_IE_R {
103        FPU_IE_R::new(((self.bits >> 26) & 0x3f) as u8)
104    }
105}
106impl core::fmt::Debug for R {
107    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
108        f.debug_struct("CFGR1")
109            .field("boosten", &self.boosten())
110            .field("anaswvdd", &self.anaswvdd())
111            .field("i2c_pb6_fmp", &self.i2c_pb6_fmp())
112            .field("i2c_pb7_fmp", &self.i2c_pb7_fmp())
113            .field("i2c_pb8_fmp", &self.i2c_pb8_fmp())
114            .field("i2c_pb9_fmp", &self.i2c_pb9_fmp())
115            .field("i2c1_fmp", &self.i2c1_fmp())
116            .field("i2c2_fmp", &self.i2c2_fmp())
117            .field("i2c3_fmp", &self.i2c3_fmp())
118            .field("i2c4_fmp", &self.i2c4_fmp())
119            .field("fpu_ie", &self.fpu_ie())
120            .finish()
121    }
122}
123impl W {
124    ///Bit 8 - BOOSTEN
125    #[inline(always)]
126    pub fn boosten(&mut self) -> BOOSTEN_W<CFGR1rs> {
127        BOOSTEN_W::new(self, 8)
128    }
129    ///Bit 9 - GPIO analog switch control voltage selection
130    #[inline(always)]
131    pub fn anaswvdd(&mut self) -> ANASWVDD_W<CFGR1rs> {
132        ANASWVDD_W::new(self, 9)
133    }
134    ///Bit 16 - FM+ drive capability on PB6
135    #[inline(always)]
136    pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<CFGR1rs> {
137        I2C_PB6_FMP_W::new(self, 16)
138    }
139    ///Bit 17 - FM+ drive capability on PB6
140    #[inline(always)]
141    pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<CFGR1rs> {
142        I2C_PB7_FMP_W::new(self, 17)
143    }
144    ///Bit 18 - FM+ drive capability on PB6
145    #[inline(always)]
146    pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<CFGR1rs> {
147        I2C_PB8_FMP_W::new(self, 18)
148    }
149    ///Bit 19 - FM+ drive capability on PB6
150    #[inline(always)]
151    pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<CFGR1rs> {
152        I2C_PB9_FMP_W::new(self, 19)
153    }
154    ///Bit 20 - I2C1 FM+ drive capability enable
155    #[inline(always)]
156    pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<CFGR1rs> {
157        I2C1_FMP_W::new(self, 20)
158    }
159    ///Bit 21 - I2C1 FM+ drive capability enable
160    #[inline(always)]
161    pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<CFGR1rs> {
162        I2C2_FMP_W::new(self, 21)
163    }
164    ///Bit 22 - I2C1 FM+ drive capability enable
165    #[inline(always)]
166    pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<CFGR1rs> {
167        I2C3_FMP_W::new(self, 22)
168    }
169    ///Bit 23 - I2C1 FM+ drive capability enable
170    #[inline(always)]
171    pub fn i2c4_fmp(&mut self) -> I2C4_FMP_W<CFGR1rs> {
172        I2C4_FMP_W::new(self, 23)
173    }
174    ///Bits 26:31 - FPU Interrupts Enable
175    #[inline(always)]
176    pub fn fpu_ie(&mut self) -> FPU_IE_W<CFGR1rs> {
177        FPU_IE_W::new(self, 26)
178    }
179}
180/**peripheral mode configuration register
181
182You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#SYSCFG:CFGR1)*/
185pub struct CFGR1rs;
186impl crate::RegisterSpec for CFGR1rs {
187    type Ux = u32;
188}
189///`read()` method returns [`cfgr1::R`](R) reader structure
190impl crate::Readable for CFGR1rs {}
191///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
192impl crate::Writable for CFGR1rs {
193    type Safety = crate::Unsafe;
194}
195///`reset()` method sets CFGR1 to value 0x7c00_0001
196impl crate::Resettable for CFGR1rs {
197    const RESET_VALUE: u32 = 0x7c00_0001;
198}
stm32g4_staging/stm32g441/syscfg/cfgr1.rs

stm32g4_staging/stm32g441/syscfg/
cfgr1.rs
