stm32g4_staging/stm32g431/usart1/
cr3.rs

1///Register `CR3` reader
2pub type R = crate::R<CR3rs>;
3///Register `CR3` writer
4pub type W = crate::W<CR3rs>;
5/**Error interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EIE {
11    ///0: Interrupt is inhibited
12    Disabled = 0,
13    ///1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
14    Enabled = 1,
15}
16impl From<EIE> for bool {
17    #[inline(always)]
18    fn from(variant: EIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EIE` reader - Error interrupt enable
23pub type EIE_R = crate::BitReader<EIE>;
24impl EIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EIE {
28        match self.bits {
29            false => EIE::Disabled,
30            true => EIE::Enabled,
31        }
32    }
33    ///Interrupt is inhibited
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EIE::Disabled
37    }
38    ///An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EIE::Enabled
42    }
43}
44///Field `EIE` writer - Error interrupt enable
45pub type EIE_W<'a, REG> = crate::BitWriter<'a, REG, EIE>;
46impl<'a, REG> EIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt is inhibited
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EIE::Disabled)
54    }
55    ///An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EIE::Enabled)
59    }
60}
61/**Ir mode enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum IREN {
67    ///0: IrDA disabled
68    Disabled = 0,
69    ///1: IrDA enabled
70    Enabled = 1,
71}
72impl From<IREN> for bool {
73    #[inline(always)]
74    fn from(variant: IREN) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `IREN` reader - Ir mode enable
79pub type IREN_R = crate::BitReader<IREN>;
80impl IREN_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> IREN {
84        match self.bits {
85            false => IREN::Disabled,
86            true => IREN::Enabled,
87        }
88    }
89    ///IrDA disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == IREN::Disabled
93    }
94    ///IrDA enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == IREN::Enabled
98    }
99}
100///Field `IREN` writer - Ir mode enable
101pub type IREN_W<'a, REG> = crate::BitWriter<'a, REG, IREN>;
102impl<'a, REG> IREN_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///IrDA disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(IREN::Disabled)
110    }
111    ///IrDA enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(IREN::Enabled)
115    }
116}
117/**Ir low-power
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum IRLP {
123    ///0: Normal mode
124    Normal = 0,
125    ///1: Low-power mode
126    LowPower = 1,
127}
128impl From<IRLP> for bool {
129    #[inline(always)]
130    fn from(variant: IRLP) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `IRLP` reader - Ir low-power
135pub type IRLP_R = crate::BitReader<IRLP>;
136impl IRLP_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> IRLP {
140        match self.bits {
141            false => IRLP::Normal,
142            true => IRLP::LowPower,
143        }
144    }
145    ///Normal mode
146    #[inline(always)]
147    pub fn is_normal(&self) -> bool {
148        *self == IRLP::Normal
149    }
150    ///Low-power mode
151    #[inline(always)]
152    pub fn is_low_power(&self) -> bool {
153        *self == IRLP::LowPower
154    }
155}
156///Field `IRLP` writer - Ir low-power
157pub type IRLP_W<'a, REG> = crate::BitWriter<'a, REG, IRLP>;
158impl<'a, REG> IRLP_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Normal mode
163    #[inline(always)]
164    pub fn normal(self) -> &'a mut crate::W<REG> {
165        self.variant(IRLP::Normal)
166    }
167    ///Low-power mode
168    #[inline(always)]
169    pub fn low_power(self) -> &'a mut crate::W<REG> {
170        self.variant(IRLP::LowPower)
171    }
172}
173/**Half-duplex selection
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum HDSEL {
179    ///0: Half duplex mode is not selected
180    NotSelected = 0,
181    ///1: Half duplex mode is selected
182    Selected = 1,
183}
184impl From<HDSEL> for bool {
185    #[inline(always)]
186    fn from(variant: HDSEL) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `HDSEL` reader - Half-duplex selection
191pub type HDSEL_R = crate::BitReader<HDSEL>;
192impl HDSEL_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> HDSEL {
196        match self.bits {
197            false => HDSEL::NotSelected,
198            true => HDSEL::Selected,
199        }
200    }
201    ///Half duplex mode is not selected
202    #[inline(always)]
203    pub fn is_not_selected(&self) -> bool {
204        *self == HDSEL::NotSelected
205    }
206    ///Half duplex mode is selected
207    #[inline(always)]
208    pub fn is_selected(&self) -> bool {
209        *self == HDSEL::Selected
210    }
211}
212///Field `HDSEL` writer - Half-duplex selection
213pub type HDSEL_W<'a, REG> = crate::BitWriter<'a, REG, HDSEL>;
214impl<'a, REG> HDSEL_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Half duplex mode is not selected
219    #[inline(always)]
220    pub fn not_selected(self) -> &'a mut crate::W<REG> {
221        self.variant(HDSEL::NotSelected)
222    }
223    ///Half duplex mode is selected
224    #[inline(always)]
225    pub fn selected(self) -> &'a mut crate::W<REG> {
226        self.variant(HDSEL::Selected)
227    }
228}
229/**Smartcard NACK enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum NACK {
235    ///0: NACK transmission in case of parity error is disabled
236    Disabled = 0,
237    ///1: NACK transmission during parity error is enabled
238    Enabled = 1,
239}
240impl From<NACK> for bool {
241    #[inline(always)]
242    fn from(variant: NACK) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `NACK` reader - Smartcard NACK enable
247pub type NACK_R = crate::BitReader<NACK>;
248impl NACK_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> NACK {
252        match self.bits {
253            false => NACK::Disabled,
254            true => NACK::Enabled,
255        }
256    }
257    ///NACK transmission in case of parity error is disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == NACK::Disabled
261    }
262    ///NACK transmission during parity error is enabled
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == NACK::Enabled
266    }
267}
268///Field `NACK` writer - Smartcard NACK enable
269pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG, NACK>;
270impl<'a, REG> NACK_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///NACK transmission in case of parity error is disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(NACK::Disabled)
278    }
279    ///NACK transmission during parity error is enabled
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(NACK::Enabled)
283    }
284}
285/**Smartcard mode enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum SCEN {
291    ///0: Smartcard Mode disabled
292    Disabled = 0,
293    ///1: Smartcard Mode enabled
294    Enabled = 1,
295}
296impl From<SCEN> for bool {
297    #[inline(always)]
298    fn from(variant: SCEN) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `SCEN` reader - Smartcard mode enable
303pub type SCEN_R = crate::BitReader<SCEN>;
304impl SCEN_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> SCEN {
308        match self.bits {
309            false => SCEN::Disabled,
310            true => SCEN::Enabled,
311        }
312    }
313    ///Smartcard Mode disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == SCEN::Disabled
317    }
318    ///Smartcard Mode enabled
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == SCEN::Enabled
322    }
323}
324///Field `SCEN` writer - Smartcard mode enable
325pub type SCEN_W<'a, REG> = crate::BitWriter<'a, REG, SCEN>;
326impl<'a, REG> SCEN_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Smartcard Mode disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(SCEN::Disabled)
334    }
335    ///Smartcard Mode enabled
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(SCEN::Enabled)
339    }
340}
341/**DMA enable receiver
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum DMAR {
347    ///0: DMA mode is disabled for reception
348    Disabled = 0,
349    ///1: DMA mode is enabled for reception
350    Enabled = 1,
351}
352impl From<DMAR> for bool {
353    #[inline(always)]
354    fn from(variant: DMAR) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `DMAR` reader - DMA enable receiver
359pub type DMAR_R = crate::BitReader<DMAR>;
360impl DMAR_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> DMAR {
364        match self.bits {
365            false => DMAR::Disabled,
366            true => DMAR::Enabled,
367        }
368    }
369    ///DMA mode is disabled for reception
370    #[inline(always)]
371    pub fn is_disabled(&self) -> bool {
372        *self == DMAR::Disabled
373    }
374    ///DMA mode is enabled for reception
375    #[inline(always)]
376    pub fn is_enabled(&self) -> bool {
377        *self == DMAR::Enabled
378    }
379}
380///Field `DMAR` writer - DMA enable receiver
381pub type DMAR_W<'a, REG> = crate::BitWriter<'a, REG, DMAR>;
382impl<'a, REG> DMAR_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///DMA mode is disabled for reception
387    #[inline(always)]
388    pub fn disabled(self) -> &'a mut crate::W<REG> {
389        self.variant(DMAR::Disabled)
390    }
391    ///DMA mode is enabled for reception
392    #[inline(always)]
393    pub fn enabled(self) -> &'a mut crate::W<REG> {
394        self.variant(DMAR::Enabled)
395    }
396}
397/**DMA enable transmitter
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum DMAT {
403    ///0: DMA mode is disabled for transmission
404    Disabled = 0,
405    ///1: DMA mode is enabled for transmission
406    Enabled = 1,
407}
408impl From<DMAT> for bool {
409    #[inline(always)]
410    fn from(variant: DMAT) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `DMAT` reader - DMA enable transmitter
415pub type DMAT_R = crate::BitReader<DMAT>;
416impl DMAT_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> DMAT {
420        match self.bits {
421            false => DMAT::Disabled,
422            true => DMAT::Enabled,
423        }
424    }
425    ///DMA mode is disabled for transmission
426    #[inline(always)]
427    pub fn is_disabled(&self) -> bool {
428        *self == DMAT::Disabled
429    }
430    ///DMA mode is enabled for transmission
431    #[inline(always)]
432    pub fn is_enabled(&self) -> bool {
433        *self == DMAT::Enabled
434    }
435}
436///Field `DMAT` writer - DMA enable transmitter
437pub type DMAT_W<'a, REG> = crate::BitWriter<'a, REG, DMAT>;
438impl<'a, REG> DMAT_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///DMA mode is disabled for transmission
443    #[inline(always)]
444    pub fn disabled(self) -> &'a mut crate::W<REG> {
445        self.variant(DMAT::Disabled)
446    }
447    ///DMA mode is enabled for transmission
448    #[inline(always)]
449    pub fn enabled(self) -> &'a mut crate::W<REG> {
450        self.variant(DMAT::Enabled)
451    }
452}
453/**RTS enable
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458pub enum RTSE {
459    ///0: RTS hardware flow control disabled
460    Disabled = 0,
461    ///1: RTS output enabled, data is only requested when there is space in the receive buffer
462    Enabled = 1,
463}
464impl From<RTSE> for bool {
465    #[inline(always)]
466    fn from(variant: RTSE) -> Self {
467        variant as u8 != 0
468    }
469}
470///Field `RTSE` reader - RTS enable
471pub type RTSE_R = crate::BitReader<RTSE>;
472impl RTSE_R {
473    ///Get enumerated values variant
474    #[inline(always)]
475    pub const fn variant(&self) -> RTSE {
476        match self.bits {
477            false => RTSE::Disabled,
478            true => RTSE::Enabled,
479        }
480    }
481    ///RTS hardware flow control disabled
482    #[inline(always)]
483    pub fn is_disabled(&self) -> bool {
484        *self == RTSE::Disabled
485    }
486    ///RTS output enabled, data is only requested when there is space in the receive buffer
487    #[inline(always)]
488    pub fn is_enabled(&self) -> bool {
489        *self == RTSE::Enabled
490    }
491}
492///Field `RTSE` writer - RTS enable
493pub type RTSE_W<'a, REG> = crate::BitWriter<'a, REG, RTSE>;
494impl<'a, REG> RTSE_W<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497{
498    ///RTS hardware flow control disabled
499    #[inline(always)]
500    pub fn disabled(self) -> &'a mut crate::W<REG> {
501        self.variant(RTSE::Disabled)
502    }
503    ///RTS output enabled, data is only requested when there is space in the receive buffer
504    #[inline(always)]
505    pub fn enabled(self) -> &'a mut crate::W<REG> {
506        self.variant(RTSE::Enabled)
507    }
508}
509/**CTS enable
510
511Value on reset: 0*/
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum CTSE {
515    ///0: CTS hardware flow control disabled
516    Disabled = 0,
517    ///1: CTS mode enabled, data is only transmitted when the CTS input is asserted
518    Enabled = 1,
519}
520impl From<CTSE> for bool {
521    #[inline(always)]
522    fn from(variant: CTSE) -> Self {
523        variant as u8 != 0
524    }
525}
526///Field `CTSE` reader - CTS enable
527pub type CTSE_R = crate::BitReader<CTSE>;
528impl CTSE_R {
529    ///Get enumerated values variant
530    #[inline(always)]
531    pub const fn variant(&self) -> CTSE {
532        match self.bits {
533            false => CTSE::Disabled,
534            true => CTSE::Enabled,
535        }
536    }
537    ///CTS hardware flow control disabled
538    #[inline(always)]
539    pub fn is_disabled(&self) -> bool {
540        *self == CTSE::Disabled
541    }
542    ///CTS mode enabled, data is only transmitted when the CTS input is asserted
543    #[inline(always)]
544    pub fn is_enabled(&self) -> bool {
545        *self == CTSE::Enabled
546    }
547}
548///Field `CTSE` writer - CTS enable
549pub type CTSE_W<'a, REG> = crate::BitWriter<'a, REG, CTSE>;
550impl<'a, REG> CTSE_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    ///CTS hardware flow control disabled
555    #[inline(always)]
556    pub fn disabled(self) -> &'a mut crate::W<REG> {
557        self.variant(CTSE::Disabled)
558    }
559    ///CTS mode enabled, data is only transmitted when the CTS input is asserted
560    #[inline(always)]
561    pub fn enabled(self) -> &'a mut crate::W<REG> {
562        self.variant(CTSE::Enabled)
563    }
564}
565/**CTS interrupt enable
566
567Value on reset: 0*/
568#[cfg_attr(feature = "defmt", derive(defmt::Format))]
569#[derive(Clone, Copy, Debug, PartialEq, Eq)]
570pub enum CTSIE {
571    ///0: Interrupt is inhibited
572    Disabled = 0,
573    ///1: An interrupt is generated whenever CTSIF=1 in the ISR register
574    Enabled = 1,
575}
576impl From<CTSIE> for bool {
577    #[inline(always)]
578    fn from(variant: CTSIE) -> Self {
579        variant as u8 != 0
580    }
581}
582///Field `CTSIE` reader - CTS interrupt enable
583pub type CTSIE_R = crate::BitReader<CTSIE>;
584impl CTSIE_R {
585    ///Get enumerated values variant
586    #[inline(always)]
587    pub const fn variant(&self) -> CTSIE {
588        match self.bits {
589            false => CTSIE::Disabled,
590            true => CTSIE::Enabled,
591        }
592    }
593    ///Interrupt is inhibited
594    #[inline(always)]
595    pub fn is_disabled(&self) -> bool {
596        *self == CTSIE::Disabled
597    }
598    ///An interrupt is generated whenever CTSIF=1 in the ISR register
599    #[inline(always)]
600    pub fn is_enabled(&self) -> bool {
601        *self == CTSIE::Enabled
602    }
603}
604///Field `CTSIE` writer - CTS interrupt enable
605pub type CTSIE_W<'a, REG> = crate::BitWriter<'a, REG, CTSIE>;
606impl<'a, REG> CTSIE_W<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609{
610    ///Interrupt is inhibited
611    #[inline(always)]
612    pub fn disabled(self) -> &'a mut crate::W<REG> {
613        self.variant(CTSIE::Disabled)
614    }
615    ///An interrupt is generated whenever CTSIF=1 in the ISR register
616    #[inline(always)]
617    pub fn enabled(self) -> &'a mut crate::W<REG> {
618        self.variant(CTSIE::Enabled)
619    }
620}
621/**One sample bit method enable
622
623Value on reset: 0*/
624#[cfg_attr(feature = "defmt", derive(defmt::Format))]
625#[derive(Clone, Copy, Debug, PartialEq, Eq)]
626pub enum ONEBIT {
627    ///0: Three sample bit method
628    Sample3 = 0,
629    ///1: One sample bit method
630    Sample1 = 1,
631}
632impl From<ONEBIT> for bool {
633    #[inline(always)]
634    fn from(variant: ONEBIT) -> Self {
635        variant as u8 != 0
636    }
637}
638///Field `ONEBIT` reader - One sample bit method enable
639pub type ONEBIT_R = crate::BitReader<ONEBIT>;
640impl ONEBIT_R {
641    ///Get enumerated values variant
642    #[inline(always)]
643    pub const fn variant(&self) -> ONEBIT {
644        match self.bits {
645            false => ONEBIT::Sample3,
646            true => ONEBIT::Sample1,
647        }
648    }
649    ///Three sample bit method
650    #[inline(always)]
651    pub fn is_sample3(&self) -> bool {
652        *self == ONEBIT::Sample3
653    }
654    ///One sample bit method
655    #[inline(always)]
656    pub fn is_sample1(&self) -> bool {
657        *self == ONEBIT::Sample1
658    }
659}
660///Field `ONEBIT` writer - One sample bit method enable
661pub type ONEBIT_W<'a, REG> = crate::BitWriter<'a, REG, ONEBIT>;
662impl<'a, REG> ONEBIT_W<'a, REG>
663where
664    REG: crate::Writable + crate::RegisterSpec,
665{
666    ///Three sample bit method
667    #[inline(always)]
668    pub fn sample3(self) -> &'a mut crate::W<REG> {
669        self.variant(ONEBIT::Sample3)
670    }
671    ///One sample bit method
672    #[inline(always)]
673    pub fn sample1(self) -> &'a mut crate::W<REG> {
674        self.variant(ONEBIT::Sample1)
675    }
676}
677/**Overrun Disable
678
679Value on reset: 0*/
680#[cfg_attr(feature = "defmt", derive(defmt::Format))]
681#[derive(Clone, Copy, Debug, PartialEq, Eq)]
682pub enum OVRDIS {
683    ///0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
684    Enabled = 0,
685    ///1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
686    Disabled = 1,
687}
688impl From<OVRDIS> for bool {
689    #[inline(always)]
690    fn from(variant: OVRDIS) -> Self {
691        variant as u8 != 0
692    }
693}
694///Field `OVRDIS` reader - Overrun Disable
695pub type OVRDIS_R = crate::BitReader<OVRDIS>;
696impl OVRDIS_R {
697    ///Get enumerated values variant
698    #[inline(always)]
699    pub const fn variant(&self) -> OVRDIS {
700        match self.bits {
701            false => OVRDIS::Enabled,
702            true => OVRDIS::Disabled,
703        }
704    }
705    ///Overrun Error Flag, ORE, is set when received data is not read before receiving new data
706    #[inline(always)]
707    pub fn is_enabled(&self) -> bool {
708        *self == OVRDIS::Enabled
709    }
710    ///Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
711    #[inline(always)]
712    pub fn is_disabled(&self) -> bool {
713        *self == OVRDIS::Disabled
714    }
715}
716///Field `OVRDIS` writer - Overrun Disable
717pub type OVRDIS_W<'a, REG> = crate::BitWriter<'a, REG, OVRDIS>;
718impl<'a, REG> OVRDIS_W<'a, REG>
719where
720    REG: crate::Writable + crate::RegisterSpec,
721{
722    ///Overrun Error Flag, ORE, is set when received data is not read before receiving new data
723    #[inline(always)]
724    pub fn enabled(self) -> &'a mut crate::W<REG> {
725        self.variant(OVRDIS::Enabled)
726    }
727    ///Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
728    #[inline(always)]
729    pub fn disabled(self) -> &'a mut crate::W<REG> {
730        self.variant(OVRDIS::Disabled)
731    }
732}
733/**DMA Disable on Reception Error
734
735Value on reset: 0*/
736#[cfg_attr(feature = "defmt", derive(defmt::Format))]
737#[derive(Clone, Copy, Debug, PartialEq, Eq)]
738pub enum DDRE {
739    ///0: DMA is not disabled in case of reception error
740    NotDisabled = 0,
741    ///1: DMA is disabled following a reception error
742    Disabled = 1,
743}
744impl From<DDRE> for bool {
745    #[inline(always)]
746    fn from(variant: DDRE) -> Self {
747        variant as u8 != 0
748    }
749}
750///Field `DDRE` reader - DMA Disable on Reception Error
751pub type DDRE_R = crate::BitReader<DDRE>;
752impl DDRE_R {
753    ///Get enumerated values variant
754    #[inline(always)]
755    pub const fn variant(&self) -> DDRE {
756        match self.bits {
757            false => DDRE::NotDisabled,
758            true => DDRE::Disabled,
759        }
760    }
761    ///DMA is not disabled in case of reception error
762    #[inline(always)]
763    pub fn is_not_disabled(&self) -> bool {
764        *self == DDRE::NotDisabled
765    }
766    ///DMA is disabled following a reception error
767    #[inline(always)]
768    pub fn is_disabled(&self) -> bool {
769        *self == DDRE::Disabled
770    }
771}
772///Field `DDRE` writer - DMA Disable on Reception Error
773pub type DDRE_W<'a, REG> = crate::BitWriter<'a, REG, DDRE>;
774impl<'a, REG> DDRE_W<'a, REG>
775where
776    REG: crate::Writable + crate::RegisterSpec,
777{
778    ///DMA is not disabled in case of reception error
779    #[inline(always)]
780    pub fn not_disabled(self) -> &'a mut crate::W<REG> {
781        self.variant(DDRE::NotDisabled)
782    }
783    ///DMA is disabled following a reception error
784    #[inline(always)]
785    pub fn disabled(self) -> &'a mut crate::W<REG> {
786        self.variant(DDRE::Disabled)
787    }
788}
789/**Driver enable mode
790
791Value on reset: 0*/
792#[cfg_attr(feature = "defmt", derive(defmt::Format))]
793#[derive(Clone, Copy, Debug, PartialEq, Eq)]
794pub enum DEM {
795    ///0: DE function is disabled
796    Disabled = 0,
797    ///1: The DE signal is output on the RTS pin
798    Enabled = 1,
799}
800impl From<DEM> for bool {
801    #[inline(always)]
802    fn from(variant: DEM) -> Self {
803        variant as u8 != 0
804    }
805}
806///Field `DEM` reader - Driver enable mode
807pub type DEM_R = crate::BitReader<DEM>;
808impl DEM_R {
809    ///Get enumerated values variant
810    #[inline(always)]
811    pub const fn variant(&self) -> DEM {
812        match self.bits {
813            false => DEM::Disabled,
814            true => DEM::Enabled,
815        }
816    }
817    ///DE function is disabled
818    #[inline(always)]
819    pub fn is_disabled(&self) -> bool {
820        *self == DEM::Disabled
821    }
822    ///The DE signal is output on the RTS pin
823    #[inline(always)]
824    pub fn is_enabled(&self) -> bool {
825        *self == DEM::Enabled
826    }
827}
828///Field `DEM` writer - Driver enable mode
829pub type DEM_W<'a, REG> = crate::BitWriter<'a, REG, DEM>;
830impl<'a, REG> DEM_W<'a, REG>
831where
832    REG: crate::Writable + crate::RegisterSpec,
833{
834    ///DE function is disabled
835    #[inline(always)]
836    pub fn disabled(self) -> &'a mut crate::W<REG> {
837        self.variant(DEM::Disabled)
838    }
839    ///The DE signal is output on the RTS pin
840    #[inline(always)]
841    pub fn enabled(self) -> &'a mut crate::W<REG> {
842        self.variant(DEM::Enabled)
843    }
844}
845/**Driver enable polarity selection
846
847Value on reset: 0*/
848#[cfg_attr(feature = "defmt", derive(defmt::Format))]
849#[derive(Clone, Copy, Debug, PartialEq, Eq)]
850pub enum DEP {
851    ///0: DE signal is active high
852    High = 0,
853    ///1: DE signal is active low
854    Low = 1,
855}
856impl From<DEP> for bool {
857    #[inline(always)]
858    fn from(variant: DEP) -> Self {
859        variant as u8 != 0
860    }
861}
862///Field `DEP` reader - Driver enable polarity selection
863pub type DEP_R = crate::BitReader<DEP>;
864impl DEP_R {
865    ///Get enumerated values variant
866    #[inline(always)]
867    pub const fn variant(&self) -> DEP {
868        match self.bits {
869            false => DEP::High,
870            true => DEP::Low,
871        }
872    }
873    ///DE signal is active high
874    #[inline(always)]
875    pub fn is_high(&self) -> bool {
876        *self == DEP::High
877    }
878    ///DE signal is active low
879    #[inline(always)]
880    pub fn is_low(&self) -> bool {
881        *self == DEP::Low
882    }
883}
884///Field `DEP` writer - Driver enable polarity selection
885pub type DEP_W<'a, REG> = crate::BitWriter<'a, REG, DEP>;
886impl<'a, REG> DEP_W<'a, REG>
887where
888    REG: crate::Writable + crate::RegisterSpec,
889{
890    ///DE signal is active high
891    #[inline(always)]
892    pub fn high(self) -> &'a mut crate::W<REG> {
893        self.variant(DEP::High)
894    }
895    ///DE signal is active low
896    #[inline(always)]
897    pub fn low(self) -> &'a mut crate::W<REG> {
898        self.variant(DEP::Low)
899    }
900}
901///Field `SCARCNT` reader - Smartcard auto-retry count
902pub type SCARCNT_R = crate::FieldReader;
903///Field `SCARCNT` writer - Smartcard auto-retry count
904pub type SCARCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
905/**Wakeup from Stop mode interrupt flag selection
906
907Value on reset: 0*/
908#[cfg_attr(feature = "defmt", derive(defmt::Format))]
909#[derive(Clone, Copy, Debug, PartialEq, Eq)]
910#[repr(u8)]
911pub enum WUS {
912    ///0: WUF active on address match
913    Address = 0,
914    ///2: WuF active on Start bit detection
915    Start = 2,
916    ///3: WUF active on RXNE
917    Rxne = 3,
918}
919impl From<WUS> for u8 {
920    #[inline(always)]
921    fn from(variant: WUS) -> Self {
922        variant as _
923    }
924}
925impl crate::FieldSpec for WUS {
926    type Ux = u8;
927}
928impl crate::IsEnum for WUS {}
929///Field `WUS` reader - Wakeup from Stop mode interrupt flag selection
930pub type WUS_R = crate::FieldReader<WUS>;
931impl WUS_R {
932    ///Get enumerated values variant
933    #[inline(always)]
934    pub const fn variant(&self) -> Option<WUS> {
935        match self.bits {
936            0 => Some(WUS::Address),
937            2 => Some(WUS::Start),
938            3 => Some(WUS::Rxne),
939            _ => None,
940        }
941    }
942    ///WUF active on address match
943    #[inline(always)]
944    pub fn is_address(&self) -> bool {
945        *self == WUS::Address
946    }
947    ///WuF active on Start bit detection
948    #[inline(always)]
949    pub fn is_start(&self) -> bool {
950        *self == WUS::Start
951    }
952    ///WUF active on RXNE
953    #[inline(always)]
954    pub fn is_rxne(&self) -> bool {
955        *self == WUS::Rxne
956    }
957}
958///Field `WUS` writer - Wakeup from Stop mode interrupt flag selection
959pub type WUS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WUS>;
960impl<'a, REG> WUS_W<'a, REG>
961where
962    REG: crate::Writable + crate::RegisterSpec,
963    REG::Ux: From<u8>,
964{
965    ///WUF active on address match
966    #[inline(always)]
967    pub fn address(self) -> &'a mut crate::W<REG> {
968        self.variant(WUS::Address)
969    }
970    ///WuF active on Start bit detection
971    #[inline(always)]
972    pub fn start(self) -> &'a mut crate::W<REG> {
973        self.variant(WUS::Start)
974    }
975    ///WUF active on RXNE
976    #[inline(always)]
977    pub fn rxne(self) -> &'a mut crate::W<REG> {
978        self.variant(WUS::Rxne)
979    }
980}
981/**Wakeup from Stop mode interrupt enable
982
983Value on reset: 0*/
984#[cfg_attr(feature = "defmt", derive(defmt::Format))]
985#[derive(Clone, Copy, Debug, PartialEq, Eq)]
986pub enum WUFIE {
987    ///0: Interrupt is inhibited
988    Disabled = 0,
989    ///1: An USART interrupt is generated whenever WUF=1 in the ISR register
990    Enabled = 1,
991}
992impl From<WUFIE> for bool {
993    #[inline(always)]
994    fn from(variant: WUFIE) -> Self {
995        variant as u8 != 0
996    }
997}
998///Field `WUFIE` reader - Wakeup from Stop mode interrupt enable
999pub type WUFIE_R = crate::BitReader<WUFIE>;
1000impl WUFIE_R {
1001    ///Get enumerated values variant
1002    #[inline(always)]
1003    pub const fn variant(&self) -> WUFIE {
1004        match self.bits {
1005            false => WUFIE::Disabled,
1006            true => WUFIE::Enabled,
1007        }
1008    }
1009    ///Interrupt is inhibited
1010    #[inline(always)]
1011    pub fn is_disabled(&self) -> bool {
1012        *self == WUFIE::Disabled
1013    }
1014    ///An USART interrupt is generated whenever WUF=1 in the ISR register
1015    #[inline(always)]
1016    pub fn is_enabled(&self) -> bool {
1017        *self == WUFIE::Enabled
1018    }
1019}
1020///Field `WUFIE` writer - Wakeup from Stop mode interrupt enable
1021pub type WUFIE_W<'a, REG> = crate::BitWriter<'a, REG, WUFIE>;
1022impl<'a, REG> WUFIE_W<'a, REG>
1023where
1024    REG: crate::Writable + crate::RegisterSpec,
1025{
1026    ///Interrupt is inhibited
1027    #[inline(always)]
1028    pub fn disabled(self) -> &'a mut crate::W<REG> {
1029        self.variant(WUFIE::Disabled)
1030    }
1031    ///An USART interrupt is generated whenever WUF=1 in the ISR register
1032    #[inline(always)]
1033    pub fn enabled(self) -> &'a mut crate::W<REG> {
1034        self.variant(WUFIE::Enabled)
1035    }
1036}
1037/**TXFTIE
1038
1039Value on reset: 0*/
1040#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1041#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1042pub enum TXFTIE {
1043    ///0: Interrupt inhibited
1044    Disabled = 0,
1045    ///1: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
1046    Enabled = 1,
1047}
1048impl From<TXFTIE> for bool {
1049    #[inline(always)]
1050    fn from(variant: TXFTIE) -> Self {
1051        variant as u8 != 0
1052    }
1053}
1054///Field `TXFTIE` reader - TXFTIE
1055pub type TXFTIE_R = crate::BitReader<TXFTIE>;
1056impl TXFTIE_R {
1057    ///Get enumerated values variant
1058    #[inline(always)]
1059    pub const fn variant(&self) -> TXFTIE {
1060        match self.bits {
1061            false => TXFTIE::Disabled,
1062            true => TXFTIE::Enabled,
1063        }
1064    }
1065    ///Interrupt inhibited
1066    #[inline(always)]
1067    pub fn is_disabled(&self) -> bool {
1068        *self == TXFTIE::Disabled
1069    }
1070    ///USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
1071    #[inline(always)]
1072    pub fn is_enabled(&self) -> bool {
1073        *self == TXFTIE::Enabled
1074    }
1075}
1076///Field `TXFTIE` writer - TXFTIE
1077pub type TXFTIE_W<'a, REG> = crate::BitWriter<'a, REG, TXFTIE>;
1078impl<'a, REG> TXFTIE_W<'a, REG>
1079where
1080    REG: crate::Writable + crate::RegisterSpec,
1081{
1082    ///Interrupt inhibited
1083    #[inline(always)]
1084    pub fn disabled(self) -> &'a mut crate::W<REG> {
1085        self.variant(TXFTIE::Disabled)
1086    }
1087    ///USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
1088    #[inline(always)]
1089    pub fn enabled(self) -> &'a mut crate::W<REG> {
1090        self.variant(TXFTIE::Enabled)
1091    }
1092}
1093/**TCBGTIE
1094
1095Value on reset: 0*/
1096#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1097#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1098pub enum TCBGTIE {
1099    ///0: Interrupt inhibited
1100    Disabled = 0,
1101    ///1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
1102    Enabled = 1,
1103}
1104impl From<TCBGTIE> for bool {
1105    #[inline(always)]
1106    fn from(variant: TCBGTIE) -> Self {
1107        variant as u8 != 0
1108    }
1109}
1110///Field `TCBGTIE` reader - TCBGTIE
1111pub type TCBGTIE_R = crate::BitReader<TCBGTIE>;
1112impl TCBGTIE_R {
1113    ///Get enumerated values variant
1114    #[inline(always)]
1115    pub const fn variant(&self) -> TCBGTIE {
1116        match self.bits {
1117            false => TCBGTIE::Disabled,
1118            true => TCBGTIE::Enabled,
1119        }
1120    }
1121    ///Interrupt inhibited
1122    #[inline(always)]
1123    pub fn is_disabled(&self) -> bool {
1124        *self == TCBGTIE::Disabled
1125    }
1126    ///USART interrupt generated whenever TCBGT=1 in the USART_ISR register
1127    #[inline(always)]
1128    pub fn is_enabled(&self) -> bool {
1129        *self == TCBGTIE::Enabled
1130    }
1131}
1132///Field `TCBGTIE` writer - TCBGTIE
1133pub type TCBGTIE_W<'a, REG> = crate::BitWriter<'a, REG, TCBGTIE>;
1134impl<'a, REG> TCBGTIE_W<'a, REG>
1135where
1136    REG: crate::Writable + crate::RegisterSpec,
1137{
1138    ///Interrupt inhibited
1139    #[inline(always)]
1140    pub fn disabled(self) -> &'a mut crate::W<REG> {
1141        self.variant(TCBGTIE::Disabled)
1142    }
1143    ///USART interrupt generated whenever TCBGT=1 in the USART_ISR register
1144    #[inline(always)]
1145    pub fn enabled(self) -> &'a mut crate::W<REG> {
1146        self.variant(TCBGTIE::Enabled)
1147    }
1148}
1149/**RXFTCFG
1150
1151Value on reset: 0*/
1152#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1153#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1154#[repr(u8)]
1155pub enum RXFTCFG {
1156    ///0: RXFIFO reaches 1/8 of its depth
1157    Depth1_8 = 0,
1158    ///1: RXFIFO reaches 1/4 of its depth
1159    Depth1_4 = 1,
1160    ///2: RXFIFO reaches 1/2 of its depth
1161    Depth1_2 = 2,
1162    ///3: RXFIFO reaches 3/4 of its depth
1163    Depth3_4 = 3,
1164    ///4: RXFIFO reaches 7/8 of its depth
1165    Depth7_8 = 4,
1166    ///5: RXFIFO becomes full
1167    Full = 5,
1168}
1169impl From<RXFTCFG> for u8 {
1170    #[inline(always)]
1171    fn from(variant: RXFTCFG) -> Self {
1172        variant as _
1173    }
1174}
1175impl crate::FieldSpec for RXFTCFG {
1176    type Ux = u8;
1177}
1178impl crate::IsEnum for RXFTCFG {}
1179///Field `RXFTCFG` reader - RXFTCFG
1180pub type RXFTCFG_R = crate::FieldReader<RXFTCFG>;
1181impl RXFTCFG_R {
1182    ///Get enumerated values variant
1183    #[inline(always)]
1184    pub const fn variant(&self) -> Option<RXFTCFG> {
1185        match self.bits {
1186            0 => Some(RXFTCFG::Depth1_8),
1187            1 => Some(RXFTCFG::Depth1_4),
1188            2 => Some(RXFTCFG::Depth1_2),
1189            3 => Some(RXFTCFG::Depth3_4),
1190            4 => Some(RXFTCFG::Depth7_8),
1191            5 => Some(RXFTCFG::Full),
1192            _ => None,
1193        }
1194    }
1195    ///RXFIFO reaches 1/8 of its depth
1196    #[inline(always)]
1197    pub fn is_depth_1_8(&self) -> bool {
1198        *self == RXFTCFG::Depth1_8
1199    }
1200    ///RXFIFO reaches 1/4 of its depth
1201    #[inline(always)]
1202    pub fn is_depth_1_4(&self) -> bool {
1203        *self == RXFTCFG::Depth1_4
1204    }
1205    ///RXFIFO reaches 1/2 of its depth
1206    #[inline(always)]
1207    pub fn is_depth_1_2(&self) -> bool {
1208        *self == RXFTCFG::Depth1_2
1209    }
1210    ///RXFIFO reaches 3/4 of its depth
1211    #[inline(always)]
1212    pub fn is_depth_3_4(&self) -> bool {
1213        *self == RXFTCFG::Depth3_4
1214    }
1215    ///RXFIFO reaches 7/8 of its depth
1216    #[inline(always)]
1217    pub fn is_depth_7_8(&self) -> bool {
1218        *self == RXFTCFG::Depth7_8
1219    }
1220    ///RXFIFO becomes full
1221    #[inline(always)]
1222    pub fn is_full(&self) -> bool {
1223        *self == RXFTCFG::Full
1224    }
1225}
1226///Field `RXFTCFG` writer - RXFTCFG
1227pub type RXFTCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3, RXFTCFG>;
1228impl<'a, REG> RXFTCFG_W<'a, REG>
1229where
1230    REG: crate::Writable + crate::RegisterSpec,
1231    REG::Ux: From<u8>,
1232{
1233    ///RXFIFO reaches 1/8 of its depth
1234    #[inline(always)]
1235    pub fn depth_1_8(self) -> &'a mut crate::W<REG> {
1236        self.variant(RXFTCFG::Depth1_8)
1237    }
1238    ///RXFIFO reaches 1/4 of its depth
1239    #[inline(always)]
1240    pub fn depth_1_4(self) -> &'a mut crate::W<REG> {
1241        self.variant(RXFTCFG::Depth1_4)
1242    }
1243    ///RXFIFO reaches 1/2 of its depth
1244    #[inline(always)]
1245    pub fn depth_1_2(self) -> &'a mut crate::W<REG> {
1246        self.variant(RXFTCFG::Depth1_2)
1247    }
1248    ///RXFIFO reaches 3/4 of its depth
1249    #[inline(always)]
1250    pub fn depth_3_4(self) -> &'a mut crate::W<REG> {
1251        self.variant(RXFTCFG::Depth3_4)
1252    }
1253    ///RXFIFO reaches 7/8 of its depth
1254    #[inline(always)]
1255    pub fn depth_7_8(self) -> &'a mut crate::W<REG> {
1256        self.variant(RXFTCFG::Depth7_8)
1257    }
1258    ///RXFIFO becomes full
1259    #[inline(always)]
1260    pub fn full(self) -> &'a mut crate::W<REG> {
1261        self.variant(RXFTCFG::Full)
1262    }
1263}
1264/**RXFTIE
1265
1266Value on reset: 0*/
1267#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1268#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1269pub enum RXFTIE {
1270    ///0: Interrupt inhibited
1271    Disabled = 0,
1272    ///1: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
1273    Enabled = 1,
1274}
1275impl From<RXFTIE> for bool {
1276    #[inline(always)]
1277    fn from(variant: RXFTIE) -> Self {
1278        variant as u8 != 0
1279    }
1280}
1281///Field `RXFTIE` reader - RXFTIE
1282pub type RXFTIE_R = crate::BitReader<RXFTIE>;
1283impl RXFTIE_R {
1284    ///Get enumerated values variant
1285    #[inline(always)]
1286    pub const fn variant(&self) -> RXFTIE {
1287        match self.bits {
1288            false => RXFTIE::Disabled,
1289            true => RXFTIE::Enabled,
1290        }
1291    }
1292    ///Interrupt inhibited
1293    #[inline(always)]
1294    pub fn is_disabled(&self) -> bool {
1295        *self == RXFTIE::Disabled
1296    }
1297    ///USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
1298    #[inline(always)]
1299    pub fn is_enabled(&self) -> bool {
1300        *self == RXFTIE::Enabled
1301    }
1302}
1303///Field `RXFTIE` writer - RXFTIE
1304pub type RXFTIE_W<'a, REG> = crate::BitWriter<'a, REG, RXFTIE>;
1305impl<'a, REG> RXFTIE_W<'a, REG>
1306where
1307    REG: crate::Writable + crate::RegisterSpec,
1308{
1309    ///Interrupt inhibited
1310    #[inline(always)]
1311    pub fn disabled(self) -> &'a mut crate::W<REG> {
1312        self.variant(RXFTIE::Disabled)
1313    }
1314    ///USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
1315    #[inline(always)]
1316    pub fn enabled(self) -> &'a mut crate::W<REG> {
1317        self.variant(RXFTIE::Enabled)
1318    }
1319}
1320/**TXFTCFG
1321
1322Value on reset: 0*/
1323#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1325#[repr(u8)]
1326pub enum TXFTCFG {
1327    ///0: TXFIFO reaches 1/8 of its depth
1328    Depth1_8 = 0,
1329    ///1: TXFIFO reaches 1/4 of its depth
1330    Depth1_4 = 1,
1331    ///2: TXFIFO reaches 1/2 of its depth
1332    Depth1_2 = 2,
1333    ///3: TXFIFO reaches 3/4 of its depth
1334    Depth3_4 = 3,
1335    ///4: TXFIFO reaches 7/8 of its depth
1336    Depth7_8 = 4,
1337    ///5: TXFIFO becomes empty
1338    Empty = 5,
1339}
1340impl From<TXFTCFG> for u8 {
1341    #[inline(always)]
1342    fn from(variant: TXFTCFG) -> Self {
1343        variant as _
1344    }
1345}
1346impl crate::FieldSpec for TXFTCFG {
1347    type Ux = u8;
1348}
1349impl crate::IsEnum for TXFTCFG {}
1350///Field `TXFTCFG` reader - TXFTCFG
1351pub type TXFTCFG_R = crate::FieldReader<TXFTCFG>;
1352impl TXFTCFG_R {
1353    ///Get enumerated values variant
1354    #[inline(always)]
1355    pub const fn variant(&self) -> Option<TXFTCFG> {
1356        match self.bits {
1357            0 => Some(TXFTCFG::Depth1_8),
1358            1 => Some(TXFTCFG::Depth1_4),
1359            2 => Some(TXFTCFG::Depth1_2),
1360            3 => Some(TXFTCFG::Depth3_4),
1361            4 => Some(TXFTCFG::Depth7_8),
1362            5 => Some(TXFTCFG::Empty),
1363            _ => None,
1364        }
1365    }
1366    ///TXFIFO reaches 1/8 of its depth
1367    #[inline(always)]
1368    pub fn is_depth_1_8(&self) -> bool {
1369        *self == TXFTCFG::Depth1_8
1370    }
1371    ///TXFIFO reaches 1/4 of its depth
1372    #[inline(always)]
1373    pub fn is_depth_1_4(&self) -> bool {
1374        *self == TXFTCFG::Depth1_4
1375    }
1376    ///TXFIFO reaches 1/2 of its depth
1377    #[inline(always)]
1378    pub fn is_depth_1_2(&self) -> bool {
1379        *self == TXFTCFG::Depth1_2
1380    }
1381    ///TXFIFO reaches 3/4 of its depth
1382    #[inline(always)]
1383    pub fn is_depth_3_4(&self) -> bool {
1384        *self == TXFTCFG::Depth3_4
1385    }
1386    ///TXFIFO reaches 7/8 of its depth
1387    #[inline(always)]
1388    pub fn is_depth_7_8(&self) -> bool {
1389        *self == TXFTCFG::Depth7_8
1390    }
1391    ///TXFIFO becomes empty
1392    #[inline(always)]
1393    pub fn is_empty(&self) -> bool {
1394        *self == TXFTCFG::Empty
1395    }
1396}
1397///Field `TXFTCFG` writer - TXFTCFG
1398pub type TXFTCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TXFTCFG>;
1399impl<'a, REG> TXFTCFG_W<'a, REG>
1400where
1401    REG: crate::Writable + crate::RegisterSpec,
1402    REG::Ux: From<u8>,
1403{
1404    ///TXFIFO reaches 1/8 of its depth
1405    #[inline(always)]
1406    pub fn depth_1_8(self) -> &'a mut crate::W<REG> {
1407        self.variant(TXFTCFG::Depth1_8)
1408    }
1409    ///TXFIFO reaches 1/4 of its depth
1410    #[inline(always)]
1411    pub fn depth_1_4(self) -> &'a mut crate::W<REG> {
1412        self.variant(TXFTCFG::Depth1_4)
1413    }
1414    ///TXFIFO reaches 1/2 of its depth
1415    #[inline(always)]
1416    pub fn depth_1_2(self) -> &'a mut crate::W<REG> {
1417        self.variant(TXFTCFG::Depth1_2)
1418    }
1419    ///TXFIFO reaches 3/4 of its depth
1420    #[inline(always)]
1421    pub fn depth_3_4(self) -> &'a mut crate::W<REG> {
1422        self.variant(TXFTCFG::Depth3_4)
1423    }
1424    ///TXFIFO reaches 7/8 of its depth
1425    #[inline(always)]
1426    pub fn depth_7_8(self) -> &'a mut crate::W<REG> {
1427        self.variant(TXFTCFG::Depth7_8)
1428    }
1429    ///TXFIFO becomes empty
1430    #[inline(always)]
1431    pub fn empty(self) -> &'a mut crate::W<REG> {
1432        self.variant(TXFTCFG::Empty)
1433    }
1434}
1435impl R {
1436    ///Bit 0 - Error interrupt enable
1437    #[inline(always)]
1438    pub fn eie(&self) -> EIE_R {
1439        EIE_R::new((self.bits & 1) != 0)
1440    }
1441    ///Bit 1 - Ir mode enable
1442    #[inline(always)]
1443    pub fn iren(&self) -> IREN_R {
1444        IREN_R::new(((self.bits >> 1) & 1) != 0)
1445    }
1446    ///Bit 2 - Ir low-power
1447    #[inline(always)]
1448    pub fn irlp(&self) -> IRLP_R {
1449        IRLP_R::new(((self.bits >> 2) & 1) != 0)
1450    }
1451    ///Bit 3 - Half-duplex selection
1452    #[inline(always)]
1453    pub fn hdsel(&self) -> HDSEL_R {
1454        HDSEL_R::new(((self.bits >> 3) & 1) != 0)
1455    }
1456    ///Bit 4 - Smartcard NACK enable
1457    #[inline(always)]
1458    pub fn nack(&self) -> NACK_R {
1459        NACK_R::new(((self.bits >> 4) & 1) != 0)
1460    }
1461    ///Bit 5 - Smartcard mode enable
1462    #[inline(always)]
1463    pub fn scen(&self) -> SCEN_R {
1464        SCEN_R::new(((self.bits >> 5) & 1) != 0)
1465    }
1466    ///Bit 6 - DMA enable receiver
1467    #[inline(always)]
1468    pub fn dmar(&self) -> DMAR_R {
1469        DMAR_R::new(((self.bits >> 6) & 1) != 0)
1470    }
1471    ///Bit 7 - DMA enable transmitter
1472    #[inline(always)]
1473    pub fn dmat(&self) -> DMAT_R {
1474        DMAT_R::new(((self.bits >> 7) & 1) != 0)
1475    }
1476    ///Bit 8 - RTS enable
1477    #[inline(always)]
1478    pub fn rtse(&self) -> RTSE_R {
1479        RTSE_R::new(((self.bits >> 8) & 1) != 0)
1480    }
1481    ///Bit 9 - CTS enable
1482    #[inline(always)]
1483    pub fn ctse(&self) -> CTSE_R {
1484        CTSE_R::new(((self.bits >> 9) & 1) != 0)
1485    }
1486    ///Bit 10 - CTS interrupt enable
1487    #[inline(always)]
1488    pub fn ctsie(&self) -> CTSIE_R {
1489        CTSIE_R::new(((self.bits >> 10) & 1) != 0)
1490    }
1491    ///Bit 11 - One sample bit method enable
1492    #[inline(always)]
1493    pub fn onebit(&self) -> ONEBIT_R {
1494        ONEBIT_R::new(((self.bits >> 11) & 1) != 0)
1495    }
1496    ///Bit 12 - Overrun Disable
1497    #[inline(always)]
1498    pub fn ovrdis(&self) -> OVRDIS_R {
1499        OVRDIS_R::new(((self.bits >> 12) & 1) != 0)
1500    }
1501    ///Bit 13 - DMA Disable on Reception Error
1502    #[inline(always)]
1503    pub fn ddre(&self) -> DDRE_R {
1504        DDRE_R::new(((self.bits >> 13) & 1) != 0)
1505    }
1506    ///Bit 14 - Driver enable mode
1507    #[inline(always)]
1508    pub fn dem(&self) -> DEM_R {
1509        DEM_R::new(((self.bits >> 14) & 1) != 0)
1510    }
1511    ///Bit 15 - Driver enable polarity selection
1512    #[inline(always)]
1513    pub fn dep(&self) -> DEP_R {
1514        DEP_R::new(((self.bits >> 15) & 1) != 0)
1515    }
1516    ///Bits 17:19 - Smartcard auto-retry count
1517    #[inline(always)]
1518    pub fn scarcnt(&self) -> SCARCNT_R {
1519        SCARCNT_R::new(((self.bits >> 17) & 7) as u8)
1520    }
1521    ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
1522    #[inline(always)]
1523    pub fn wus(&self) -> WUS_R {
1524        WUS_R::new(((self.bits >> 20) & 3) as u8)
1525    }
1526    ///Bit 22 - Wakeup from Stop mode interrupt enable
1527    #[inline(always)]
1528    pub fn wufie(&self) -> WUFIE_R {
1529        WUFIE_R::new(((self.bits >> 22) & 1) != 0)
1530    }
1531    ///Bit 23 - TXFTIE
1532    #[inline(always)]
1533    pub fn txftie(&self) -> TXFTIE_R {
1534        TXFTIE_R::new(((self.bits >> 23) & 1) != 0)
1535    }
1536    ///Bit 24 - TCBGTIE
1537    #[inline(always)]
1538    pub fn tcbgtie(&self) -> TCBGTIE_R {
1539        TCBGTIE_R::new(((self.bits >> 24) & 1) != 0)
1540    }
1541    ///Bits 25:27 - RXFTCFG
1542    #[inline(always)]
1543    pub fn rxftcfg(&self) -> RXFTCFG_R {
1544        RXFTCFG_R::new(((self.bits >> 25) & 7) as u8)
1545    }
1546    ///Bit 28 - RXFTIE
1547    #[inline(always)]
1548    pub fn rxftie(&self) -> RXFTIE_R {
1549        RXFTIE_R::new(((self.bits >> 28) & 1) != 0)
1550    }
1551    ///Bits 29:31 - TXFTCFG
1552    #[inline(always)]
1553    pub fn txftcfg(&self) -> TXFTCFG_R {
1554        TXFTCFG_R::new(((self.bits >> 29) & 7) as u8)
1555    }
1556}
1557impl core::fmt::Debug for R {
1558    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1559        f.debug_struct("CR3")
1560            .field("txftcfg", &self.txftcfg())
1561            .field("rxftie", &self.rxftie())
1562            .field("rxftcfg", &self.rxftcfg())
1563            .field("tcbgtie", &self.tcbgtie())
1564            .field("txftie", &self.txftie())
1565            .field("wufie", &self.wufie())
1566            .field("wus", &self.wus())
1567            .field("scarcnt", &self.scarcnt())
1568            .field("dep", &self.dep())
1569            .field("dem", &self.dem())
1570            .field("ddre", &self.ddre())
1571            .field("ovrdis", &self.ovrdis())
1572            .field("onebit", &self.onebit())
1573            .field("ctsie", &self.ctsie())
1574            .field("ctse", &self.ctse())
1575            .field("rtse", &self.rtse())
1576            .field("dmat", &self.dmat())
1577            .field("dmar", &self.dmar())
1578            .field("scen", &self.scen())
1579            .field("nack", &self.nack())
1580            .field("hdsel", &self.hdsel())
1581            .field("irlp", &self.irlp())
1582            .field("iren", &self.iren())
1583            .field("eie", &self.eie())
1584            .finish()
1585    }
1586}
1587impl W {
1588    ///Bit 0 - Error interrupt enable
1589    #[inline(always)]
1590    pub fn eie(&mut self) -> EIE_W<CR3rs> {
1591        EIE_W::new(self, 0)
1592    }
1593    ///Bit 1 - Ir mode enable
1594    #[inline(always)]
1595    pub fn iren(&mut self) -> IREN_W<CR3rs> {
1596        IREN_W::new(self, 1)
1597    }
1598    ///Bit 2 - Ir low-power
1599    #[inline(always)]
1600    pub fn irlp(&mut self) -> IRLP_W<CR3rs> {
1601        IRLP_W::new(self, 2)
1602    }
1603    ///Bit 3 - Half-duplex selection
1604    #[inline(always)]
1605    pub fn hdsel(&mut self) -> HDSEL_W<CR3rs> {
1606        HDSEL_W::new(self, 3)
1607    }
1608    ///Bit 4 - Smartcard NACK enable
1609    #[inline(always)]
1610    pub fn nack(&mut self) -> NACK_W<CR3rs> {
1611        NACK_W::new(self, 4)
1612    }
1613    ///Bit 5 - Smartcard mode enable
1614    #[inline(always)]
1615    pub fn scen(&mut self) -> SCEN_W<CR3rs> {
1616        SCEN_W::new(self, 5)
1617    }
1618    ///Bit 6 - DMA enable receiver
1619    #[inline(always)]
1620    pub fn dmar(&mut self) -> DMAR_W<CR3rs> {
1621        DMAR_W::new(self, 6)
1622    }
1623    ///Bit 7 - DMA enable transmitter
1624    #[inline(always)]
1625    pub fn dmat(&mut self) -> DMAT_W<CR3rs> {
1626        DMAT_W::new(self, 7)
1627    }
1628    ///Bit 8 - RTS enable
1629    #[inline(always)]
1630    pub fn rtse(&mut self) -> RTSE_W<CR3rs> {
1631        RTSE_W::new(self, 8)
1632    }
1633    ///Bit 9 - CTS enable
1634    #[inline(always)]
1635    pub fn ctse(&mut self) -> CTSE_W<CR3rs> {
1636        CTSE_W::new(self, 9)
1637    }
1638    ///Bit 10 - CTS interrupt enable
1639    #[inline(always)]
1640    pub fn ctsie(&mut self) -> CTSIE_W<CR3rs> {
1641        CTSIE_W::new(self, 10)
1642    }
1643    ///Bit 11 - One sample bit method enable
1644    #[inline(always)]
1645    pub fn onebit(&mut self) -> ONEBIT_W<CR3rs> {
1646        ONEBIT_W::new(self, 11)
1647    }
1648    ///Bit 12 - Overrun Disable
1649    #[inline(always)]
1650    pub fn ovrdis(&mut self) -> OVRDIS_W<CR3rs> {
1651        OVRDIS_W::new(self, 12)
1652    }
1653    ///Bit 13 - DMA Disable on Reception Error
1654    #[inline(always)]
1655    pub fn ddre(&mut self) -> DDRE_W<CR3rs> {
1656        DDRE_W::new(self, 13)
1657    }
1658    ///Bit 14 - Driver enable mode
1659    #[inline(always)]
1660    pub fn dem(&mut self) -> DEM_W<CR3rs> {
1661        DEM_W::new(self, 14)
1662    }
1663    ///Bit 15 - Driver enable polarity selection
1664    #[inline(always)]
1665    pub fn dep(&mut self) -> DEP_W<CR3rs> {
1666        DEP_W::new(self, 15)
1667    }
1668    ///Bits 17:19 - Smartcard auto-retry count
1669    #[inline(always)]
1670    pub fn scarcnt(&mut self) -> SCARCNT_W<CR3rs> {
1671        SCARCNT_W::new(self, 17)
1672    }
1673    ///Bits 20:21 - Wakeup from Stop mode interrupt flag selection
1674    #[inline(always)]
1675    pub fn wus(&mut self) -> WUS_W<CR3rs> {
1676        WUS_W::new(self, 20)
1677    }
1678    ///Bit 22 - Wakeup from Stop mode interrupt enable
1679    #[inline(always)]
1680    pub fn wufie(&mut self) -> WUFIE_W<CR3rs> {
1681        WUFIE_W::new(self, 22)
1682    }
1683    ///Bit 23 - TXFTIE
1684    #[inline(always)]
1685    pub fn txftie(&mut self) -> TXFTIE_W<CR3rs> {
1686        TXFTIE_W::new(self, 23)
1687    }
1688    ///Bit 24 - TCBGTIE
1689    #[inline(always)]
1690    pub fn tcbgtie(&mut self) -> TCBGTIE_W<CR3rs> {
1691        TCBGTIE_W::new(self, 24)
1692    }
1693    ///Bits 25:27 - RXFTCFG
1694    #[inline(always)]
1695    pub fn rxftcfg(&mut self) -> RXFTCFG_W<CR3rs> {
1696        RXFTCFG_W::new(self, 25)
1697    }
1698    ///Bit 28 - RXFTIE
1699    #[inline(always)]
1700    pub fn rxftie(&mut self) -> RXFTIE_W<CR3rs> {
1701        RXFTIE_W::new(self, 28)
1702    }
1703    ///Bits 29:31 - TXFTCFG
1704    #[inline(always)]
1705    pub fn txftcfg(&mut self) -> TXFTCFG_W<CR3rs> {
1706        TXFTCFG_W::new(self, 29)
1707    }
1708}
1709/**Control register 3
1710
1711You can [`read`](crate::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1712
1713See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#USART1:CR3)*/
1714pub struct CR3rs;
1715impl crate::RegisterSpec for CR3rs {
1716    type Ux = u32;
1717}
1718///`read()` method returns [`cr3::R`](R) reader structure
1719impl crate::Readable for CR3rs {}
1720///`write(|w| ..)` method takes [`cr3::W`](W) writer structure
1721impl crate::Writable for CR3rs {
1722    type Safety = crate::Unsafe;
1723}
1724///`reset()` method sets CR3 to value 0
1725impl crate::Resettable for CR3rs {}
stm32g4_staging/stm32g431/usart1/cr3.rs

stm32g4_staging/stm32g431/usart1/
cr3.rs
