stm32g4_staging/stm32g431/gpioc/
ospeedr.rs

1///Register `OSPEEDR` reader
2pub type R = crate::R<OSPEEDRrs>;
3///Register `OSPEEDR` writer
4pub type W = crate::W<OSPEEDRrs>;
5///Field `OSPEEDR(0-15)` reader - Port x configuration pin %s
6pub use crate::stm32g431::gpioa::ospeedr::OSPEEDR_R;
7///Field `OSPEEDR(0-15)` writer - Port x configuration pin %s
8pub use crate::stm32g431::gpioa::ospeedr::OSPEEDR_W;
9///Port x configuration pin %s
10pub use crate::stm32g431::gpioa::ospeedr::OUTPUT_SPEED;
11impl R {
12    ///Port x configuration pin (0-15)
13    ///
14    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
15    #[inline(always)]
16    pub fn ospeedr(&self, n: u8) -> OSPEEDR_R {
17        #[allow(clippy::no_effect)] [(); 16][n as usize];
18        OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8)
19    }
20    ///Iterator for array of:
21    ///Port x configuration pin (0-15)
22    #[inline(always)]
23    pub fn ospeedr_iter(&self) -> impl Iterator<Item = OSPEEDR_R> + '_ {
24        (0..16).map(move |n| OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8))
25    }
26    ///Bits 0:1 - Port x configuration pin 0
27    #[inline(always)]
28    pub fn ospeedr0(&self) -> OSPEEDR_R {
29        OSPEEDR_R::new((self.bits & 3) as u8)
30    }
31    ///Bits 2:3 - Port x configuration pin 1
32    #[inline(always)]
33    pub fn ospeedr1(&self) -> OSPEEDR_R {
34        OSPEEDR_R::new(((self.bits >> 2) & 3) as u8)
35    }
36    ///Bits 4:5 - Port x configuration pin 2
37    #[inline(always)]
38    pub fn ospeedr2(&self) -> OSPEEDR_R {
39        OSPEEDR_R::new(((self.bits >> 4) & 3) as u8)
40    }
41    ///Bits 6:7 - Port x configuration pin 3
42    #[inline(always)]
43    pub fn ospeedr3(&self) -> OSPEEDR_R {
44        OSPEEDR_R::new(((self.bits >> 6) & 3) as u8)
45    }
46    ///Bits 8:9 - Port x configuration pin 4
47    #[inline(always)]
48    pub fn ospeedr4(&self) -> OSPEEDR_R {
49        OSPEEDR_R::new(((self.bits >> 8) & 3) as u8)
50    }
51    ///Bits 10:11 - Port x configuration pin 5
52    #[inline(always)]
53    pub fn ospeedr5(&self) -> OSPEEDR_R {
54        OSPEEDR_R::new(((self.bits >> 10) & 3) as u8)
55    }
56    ///Bits 12:13 - Port x configuration pin 6
57    #[inline(always)]
58    pub fn ospeedr6(&self) -> OSPEEDR_R {
59        OSPEEDR_R::new(((self.bits >> 12) & 3) as u8)
60    }
61    ///Bits 14:15 - Port x configuration pin 7
62    #[inline(always)]
63    pub fn ospeedr7(&self) -> OSPEEDR_R {
64        OSPEEDR_R::new(((self.bits >> 14) & 3) as u8)
65    }
66    ///Bits 16:17 - Port x configuration pin 8
67    #[inline(always)]
68    pub fn ospeedr8(&self) -> OSPEEDR_R {
69        OSPEEDR_R::new(((self.bits >> 16) & 3) as u8)
70    }
71    ///Bits 18:19 - Port x configuration pin 9
72    #[inline(always)]
73    pub fn ospeedr9(&self) -> OSPEEDR_R {
74        OSPEEDR_R::new(((self.bits >> 18) & 3) as u8)
75    }
76    ///Bits 20:21 - Port x configuration pin 10
77    #[inline(always)]
78    pub fn ospeedr10(&self) -> OSPEEDR_R {
79        OSPEEDR_R::new(((self.bits >> 20) & 3) as u8)
80    }
81    ///Bits 22:23 - Port x configuration pin 11
82    #[inline(always)]
83    pub fn ospeedr11(&self) -> OSPEEDR_R {
84        OSPEEDR_R::new(((self.bits >> 22) & 3) as u8)
85    }
86    ///Bits 24:25 - Port x configuration pin 12
87    #[inline(always)]
88    pub fn ospeedr12(&self) -> OSPEEDR_R {
89        OSPEEDR_R::new(((self.bits >> 24) & 3) as u8)
90    }
91    ///Bits 26:27 - Port x configuration pin 13
92    #[inline(always)]
93    pub fn ospeedr13(&self) -> OSPEEDR_R {
94        OSPEEDR_R::new(((self.bits >> 26) & 3) as u8)
95    }
96    ///Bits 28:29 - Port x configuration pin 14
97    #[inline(always)]
98    pub fn ospeedr14(&self) -> OSPEEDR_R {
99        OSPEEDR_R::new(((self.bits >> 28) & 3) as u8)
100    }
101    ///Bits 30:31 - Port x configuration pin 15
102    #[inline(always)]
103    pub fn ospeedr15(&self) -> OSPEEDR_R {
104        OSPEEDR_R::new(((self.bits >> 30) & 3) as u8)
105    }
106}
107impl core::fmt::Debug for R {
108    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109        f.debug_struct("OSPEEDR")
110            .field("ospeedr0", &self.ospeedr0())
111            .field("ospeedr1", &self.ospeedr1())
112            .field("ospeedr2", &self.ospeedr2())
113            .field("ospeedr3", &self.ospeedr3())
114            .field("ospeedr4", &self.ospeedr4())
115            .field("ospeedr5", &self.ospeedr5())
116            .field("ospeedr6", &self.ospeedr6())
117            .field("ospeedr7", &self.ospeedr7())
118            .field("ospeedr8", &self.ospeedr8())
119            .field("ospeedr9", &self.ospeedr9())
120            .field("ospeedr10", &self.ospeedr10())
121            .field("ospeedr11", &self.ospeedr11())
122            .field("ospeedr12", &self.ospeedr12())
123            .field("ospeedr13", &self.ospeedr13())
124            .field("ospeedr14", &self.ospeedr14())
125            .field("ospeedr15", &self.ospeedr15())
126            .finish()
127    }
128}
129impl W {
130    ///Port x configuration pin (0-15)
131    ///
132    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
133    #[inline(always)]
134    pub fn ospeedr(&mut self, n: u8) -> OSPEEDR_W<OSPEEDRrs> {
135        #[allow(clippy::no_effect)] [(); 16][n as usize];
136        OSPEEDR_W::new(self, n * 2)
137    }
138    ///Bits 0:1 - Port x configuration pin 0
139    #[inline(always)]
140    pub fn ospeedr0(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
141        OSPEEDR_W::new(self, 0)
142    }
143    ///Bits 2:3 - Port x configuration pin 1
144    #[inline(always)]
145    pub fn ospeedr1(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
146        OSPEEDR_W::new(self, 2)
147    }
148    ///Bits 4:5 - Port x configuration pin 2
149    #[inline(always)]
150    pub fn ospeedr2(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
151        OSPEEDR_W::new(self, 4)
152    }
153    ///Bits 6:7 - Port x configuration pin 3
154    #[inline(always)]
155    pub fn ospeedr3(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
156        OSPEEDR_W::new(self, 6)
157    }
158    ///Bits 8:9 - Port x configuration pin 4
159    #[inline(always)]
160    pub fn ospeedr4(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
161        OSPEEDR_W::new(self, 8)
162    }
163    ///Bits 10:11 - Port x configuration pin 5
164    #[inline(always)]
165    pub fn ospeedr5(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
166        OSPEEDR_W::new(self, 10)
167    }
168    ///Bits 12:13 - Port x configuration pin 6
169    #[inline(always)]
170    pub fn ospeedr6(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
171        OSPEEDR_W::new(self, 12)
172    }
173    ///Bits 14:15 - Port x configuration pin 7
174    #[inline(always)]
175    pub fn ospeedr7(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
176        OSPEEDR_W::new(self, 14)
177    }
178    ///Bits 16:17 - Port x configuration pin 8
179    #[inline(always)]
180    pub fn ospeedr8(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
181        OSPEEDR_W::new(self, 16)
182    }
183    ///Bits 18:19 - Port x configuration pin 9
184    #[inline(always)]
185    pub fn ospeedr9(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
186        OSPEEDR_W::new(self, 18)
187    }
188    ///Bits 20:21 - Port x configuration pin 10
189    #[inline(always)]
190    pub fn ospeedr10(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
191        OSPEEDR_W::new(self, 20)
192    }
193    ///Bits 22:23 - Port x configuration pin 11
194    #[inline(always)]
195    pub fn ospeedr11(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
196        OSPEEDR_W::new(self, 22)
197    }
198    ///Bits 24:25 - Port x configuration pin 12
199    #[inline(always)]
200    pub fn ospeedr12(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
201        OSPEEDR_W::new(self, 24)
202    }
203    ///Bits 26:27 - Port x configuration pin 13
204    #[inline(always)]
205    pub fn ospeedr13(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
206        OSPEEDR_W::new(self, 26)
207    }
208    ///Bits 28:29 - Port x configuration pin 14
209    #[inline(always)]
210    pub fn ospeedr14(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
211        OSPEEDR_W::new(self, 28)
212    }
213    ///Bits 30:31 - Port x configuration pin 15
214    #[inline(always)]
215    pub fn ospeedr15(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
216        OSPEEDR_W::new(self, 30)
217    }
218}
219/**GPIO port output speed register
220
221You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#GPIOC:OSPEEDR)*/
224pub struct OSPEEDRrs;
225impl crate::RegisterSpec for OSPEEDRrs {
226    type Ux = u32;
227}
228///`read()` method returns [`ospeedr::R`](R) reader structure
229impl crate::Readable for OSPEEDRrs {}
230///`write(|w| ..)` method takes [`ospeedr::W`](W) writer structure
231impl crate::Writable for OSPEEDRrs {
232    type Safety = crate::Unsafe;
233}
234///`reset()` method sets OSPEEDR to value 0
235impl crate::Resettable for OSPEEDRrs {}
stm32g4_staging/stm32g431/gpioc/ospeedr.rs

stm32g4_staging/stm32g431/gpioc/
ospeedr.rs
