stm32g4_staging/stm32g474/uart4/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**USART enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UE {
11    ///0: UART is disabled
12    Disabled = 0,
13    ///1: UART is enabled
14    Enabled = 1,
15}
16impl From<UE> for bool {
17    #[inline(always)]
18    fn from(variant: UE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UE` reader - USART enable
23pub type UE_R = crate::BitReader<UE>;
24impl UE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UE {
28        match self.bits {
29            false => UE::Disabled,
30            true => UE::Enabled,
31        }
32    }
33    ///UART is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UE::Disabled
37    }
38    ///UART is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UE::Enabled
42    }
43}
44///Field `UE` writer - USART enable
45pub type UE_W<'a, REG> = crate::BitWriter<'a, REG, UE>;
46impl<'a, REG> UE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///UART is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UE::Disabled)
54    }
55    ///UART is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UE::Enabled)
59    }
60}
61/**USART enable in Stop mode
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum UESM {
67    ///0: USART not able to wake up the MCU from Stop mode
68    Disabled = 0,
69    ///1: USART able to wake up the MCU from Stop mode
70    Enabled = 1,
71}
72impl From<UESM> for bool {
73    #[inline(always)]
74    fn from(variant: UESM) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `UESM` reader - USART enable in Stop mode
79pub type UESM_R = crate::BitReader<UESM>;
80impl UESM_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> UESM {
84        match self.bits {
85            false => UESM::Disabled,
86            true => UESM::Enabled,
87        }
88    }
89    ///USART not able to wake up the MCU from Stop mode
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == UESM::Disabled
93    }
94    ///USART able to wake up the MCU from Stop mode
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == UESM::Enabled
98    }
99}
100///Field `UESM` writer - USART enable in Stop mode
101pub type UESM_W<'a, REG> = crate::BitWriter<'a, REG, UESM>;
102impl<'a, REG> UESM_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///USART not able to wake up the MCU from Stop mode
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(UESM::Disabled)
110    }
111    ///USART able to wake up the MCU from Stop mode
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(UESM::Enabled)
115    }
116}
117/**Receiver enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum RE {
123    ///0: Receiver is disabled
124    Disabled = 0,
125    ///1: Receiver is enabled
126    Enabled = 1,
127}
128impl From<RE> for bool {
129    #[inline(always)]
130    fn from(variant: RE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `RE` reader - Receiver enable
135pub type RE_R = crate::BitReader<RE>;
136impl RE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> RE {
140        match self.bits {
141            false => RE::Disabled,
142            true => RE::Enabled,
143        }
144    }
145    ///Receiver is disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == RE::Disabled
149    }
150    ///Receiver is enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == RE::Enabled
154    }
155}
156///Field `RE` writer - Receiver enable
157pub type RE_W<'a, REG> = crate::BitWriter<'a, REG, RE>;
158impl<'a, REG> RE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Receiver is disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(RE::Disabled)
166    }
167    ///Receiver is enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(RE::Enabled)
171    }
172}
173/**Transmitter enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum TE {
179    ///0: Transmitter is disabled
180    Disabled = 0,
181    ///1: Transmitter is enabled
182    Enabled = 1,
183}
184impl From<TE> for bool {
185    #[inline(always)]
186    fn from(variant: TE) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `TE` reader - Transmitter enable
191pub type TE_R = crate::BitReader<TE>;
192impl TE_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> TE {
196        match self.bits {
197            false => TE::Disabled,
198            true => TE::Enabled,
199        }
200    }
201    ///Transmitter is disabled
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == TE::Disabled
205    }
206    ///Transmitter is enabled
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == TE::Enabled
210    }
211}
212///Field `TE` writer - Transmitter enable
213pub type TE_W<'a, REG> = crate::BitWriter<'a, REG, TE>;
214impl<'a, REG> TE_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Transmitter is disabled
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(TE::Disabled)
222    }
223    ///Transmitter is enabled
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(TE::Enabled)
227    }
228}
229/**IDLE interrupt enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum IDLEIE {
235    ///0: Interrupt is disabled
236    Disabled = 0,
237    ///1: Interrupt is generated whenever IDLE=1 in the ISR register
238    Enabled = 1,
239}
240impl From<IDLEIE> for bool {
241    #[inline(always)]
242    fn from(variant: IDLEIE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `IDLEIE` reader - IDLE interrupt enable
247pub type IDLEIE_R = crate::BitReader<IDLEIE>;
248impl IDLEIE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> IDLEIE {
252        match self.bits {
253            false => IDLEIE::Disabled,
254            true => IDLEIE::Enabled,
255        }
256    }
257    ///Interrupt is disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == IDLEIE::Disabled
261    }
262    ///Interrupt is generated whenever IDLE=1 in the ISR register
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == IDLEIE::Enabled
266    }
267}
268///Field `IDLEIE` writer - IDLE interrupt enable
269pub type IDLEIE_W<'a, REG> = crate::BitWriter<'a, REG, IDLEIE>;
270impl<'a, REG> IDLEIE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///Interrupt is disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(IDLEIE::Disabled)
278    }
279    ///Interrupt is generated whenever IDLE=1 in the ISR register
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(IDLEIE::Enabled)
283    }
284}
285/**RXNE interrupt enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum RXNEIE {
291    ///0: Interrupt is disabled
292    Disabled = 0,
293    ///1: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
294    Enabled = 1,
295}
296impl From<RXNEIE> for bool {
297    #[inline(always)]
298    fn from(variant: RXNEIE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `RXNEIE` reader - RXNE interrupt enable
303pub type RXNEIE_R = crate::BitReader<RXNEIE>;
304impl RXNEIE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> RXNEIE {
308        match self.bits {
309            false => RXNEIE::Disabled,
310            true => RXNEIE::Enabled,
311        }
312    }
313    ///Interrupt is disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == RXNEIE::Disabled
317    }
318    ///Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == RXNEIE::Enabled
322    }
323}
324///Field `RXNEIE` writer - RXNE interrupt enable
325pub type RXNEIE_W<'a, REG> = crate::BitWriter<'a, REG, RXNEIE>;
326impl<'a, REG> RXNEIE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Interrupt is disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(RXNEIE::Disabled)
334    }
335    ///Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(RXNEIE::Enabled)
339    }
340}
341/**Transmission complete interrupt enable
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum TCIE {
347    ///0: Interrupt is disabled
348    Disabled = 0,
349    ///1: Interrupt is generated whenever TC=1 in the ISR register
350    Enabled = 1,
351}
352impl From<TCIE> for bool {
353    #[inline(always)]
354    fn from(variant: TCIE) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `TCIE` reader - Transmission complete interrupt enable
359pub type TCIE_R = crate::BitReader<TCIE>;
360impl TCIE_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> TCIE {
364        match self.bits {
365            false => TCIE::Disabled,
366            true => TCIE::Enabled,
367        }
368    }
369    ///Interrupt is disabled
370    #[inline(always)]
371    pub fn is_disabled(&self) -> bool {
372        *self == TCIE::Disabled
373    }
374    ///Interrupt is generated whenever TC=1 in the ISR register
375    #[inline(always)]
376    pub fn is_enabled(&self) -> bool {
377        *self == TCIE::Enabled
378    }
379}
380///Field `TCIE` writer - Transmission complete interrupt enable
381pub type TCIE_W<'a, REG> = crate::BitWriter<'a, REG, TCIE>;
382impl<'a, REG> TCIE_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///Interrupt is disabled
387    #[inline(always)]
388    pub fn disabled(self) -> &'a mut crate::W<REG> {
389        self.variant(TCIE::Disabled)
390    }
391    ///Interrupt is generated whenever TC=1 in the ISR register
392    #[inline(always)]
393    pub fn enabled(self) -> &'a mut crate::W<REG> {
394        self.variant(TCIE::Enabled)
395    }
396}
397/**interrupt enable
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum TXEIE {
403    ///0: Interrupt is disabled
404    Disabled = 0,
405    ///1: Interrupt is generated whenever TXE=1 in the ISR register
406    Enabled = 1,
407}
408impl From<TXEIE> for bool {
409    #[inline(always)]
410    fn from(variant: TXEIE) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `TXEIE` reader - interrupt enable
415pub type TXEIE_R = crate::BitReader<TXEIE>;
416impl TXEIE_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> TXEIE {
420        match self.bits {
421            false => TXEIE::Disabled,
422            true => TXEIE::Enabled,
423        }
424    }
425    ///Interrupt is disabled
426    #[inline(always)]
427    pub fn is_disabled(&self) -> bool {
428        *self == TXEIE::Disabled
429    }
430    ///Interrupt is generated whenever TXE=1 in the ISR register
431    #[inline(always)]
432    pub fn is_enabled(&self) -> bool {
433        *self == TXEIE::Enabled
434    }
435}
436///Field `TXEIE` writer - interrupt enable
437pub type TXEIE_W<'a, REG> = crate::BitWriter<'a, REG, TXEIE>;
438impl<'a, REG> TXEIE_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///Interrupt is disabled
443    #[inline(always)]
444    pub fn disabled(self) -> &'a mut crate::W<REG> {
445        self.variant(TXEIE::Disabled)
446    }
447    ///Interrupt is generated whenever TXE=1 in the ISR register
448    #[inline(always)]
449    pub fn enabled(self) -> &'a mut crate::W<REG> {
450        self.variant(TXEIE::Enabled)
451    }
452}
453/**PE interrupt enable
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458pub enum PEIE {
459    ///0: Interrupt is disabled
460    Disabled = 0,
461    ///1: Interrupt is generated whenever PE=1 in the ISR register
462    Enabled = 1,
463}
464impl From<PEIE> for bool {
465    #[inline(always)]
466    fn from(variant: PEIE) -> Self {
467        variant as u8 != 0
468    }
469}
470///Field `PEIE` reader - PE interrupt enable
471pub type PEIE_R = crate::BitReader<PEIE>;
472impl PEIE_R {
473    ///Get enumerated values variant
474    #[inline(always)]
475    pub const fn variant(&self) -> PEIE {
476        match self.bits {
477            false => PEIE::Disabled,
478            true => PEIE::Enabled,
479        }
480    }
481    ///Interrupt is disabled
482    #[inline(always)]
483    pub fn is_disabled(&self) -> bool {
484        *self == PEIE::Disabled
485    }
486    ///Interrupt is generated whenever PE=1 in the ISR register
487    #[inline(always)]
488    pub fn is_enabled(&self) -> bool {
489        *self == PEIE::Enabled
490    }
491}
492///Field `PEIE` writer - PE interrupt enable
493pub type PEIE_W<'a, REG> = crate::BitWriter<'a, REG, PEIE>;
494impl<'a, REG> PEIE_W<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497{
498    ///Interrupt is disabled
499    #[inline(always)]
500    pub fn disabled(self) -> &'a mut crate::W<REG> {
501        self.variant(PEIE::Disabled)
502    }
503    ///Interrupt is generated whenever PE=1 in the ISR register
504    #[inline(always)]
505    pub fn enabled(self) -> &'a mut crate::W<REG> {
506        self.variant(PEIE::Enabled)
507    }
508}
509/**Parity selection
510
511Value on reset: 0*/
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum PS {
515    ///0: Even parity
516    Even = 0,
517    ///1: Odd parity
518    Odd = 1,
519}
520impl From<PS> for bool {
521    #[inline(always)]
522    fn from(variant: PS) -> Self {
523        variant as u8 != 0
524    }
525}
526///Field `PS` reader - Parity selection
527pub type PS_R = crate::BitReader<PS>;
528impl PS_R {
529    ///Get enumerated values variant
530    #[inline(always)]
531    pub const fn variant(&self) -> PS {
532        match self.bits {
533            false => PS::Even,
534            true => PS::Odd,
535        }
536    }
537    ///Even parity
538    #[inline(always)]
539    pub fn is_even(&self) -> bool {
540        *self == PS::Even
541    }
542    ///Odd parity
543    #[inline(always)]
544    pub fn is_odd(&self) -> bool {
545        *self == PS::Odd
546    }
547}
548///Field `PS` writer - Parity selection
549pub type PS_W<'a, REG> = crate::BitWriter<'a, REG, PS>;
550impl<'a, REG> PS_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    ///Even parity
555    #[inline(always)]
556    pub fn even(self) -> &'a mut crate::W<REG> {
557        self.variant(PS::Even)
558    }
559    ///Odd parity
560    #[inline(always)]
561    pub fn odd(self) -> &'a mut crate::W<REG> {
562        self.variant(PS::Odd)
563    }
564}
565/**Parity control enable
566
567Value on reset: 0*/
568#[cfg_attr(feature = "defmt", derive(defmt::Format))]
569#[derive(Clone, Copy, Debug, PartialEq, Eq)]
570pub enum PCE {
571    ///0: Parity control disabled
572    Disabled = 0,
573    ///1: Parity control enabled
574    Enabled = 1,
575}
576impl From<PCE> for bool {
577    #[inline(always)]
578    fn from(variant: PCE) -> Self {
579        variant as u8 != 0
580    }
581}
582///Field `PCE` reader - Parity control enable
583pub type PCE_R = crate::BitReader<PCE>;
584impl PCE_R {
585    ///Get enumerated values variant
586    #[inline(always)]
587    pub const fn variant(&self) -> PCE {
588        match self.bits {
589            false => PCE::Disabled,
590            true => PCE::Enabled,
591        }
592    }
593    ///Parity control disabled
594    #[inline(always)]
595    pub fn is_disabled(&self) -> bool {
596        *self == PCE::Disabled
597    }
598    ///Parity control enabled
599    #[inline(always)]
600    pub fn is_enabled(&self) -> bool {
601        *self == PCE::Enabled
602    }
603}
604///Field `PCE` writer - Parity control enable
605pub type PCE_W<'a, REG> = crate::BitWriter<'a, REG, PCE>;
606impl<'a, REG> PCE_W<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609{
610    ///Parity control disabled
611    #[inline(always)]
612    pub fn disabled(self) -> &'a mut crate::W<REG> {
613        self.variant(PCE::Disabled)
614    }
615    ///Parity control enabled
616    #[inline(always)]
617    pub fn enabled(self) -> &'a mut crate::W<REG> {
618        self.variant(PCE::Enabled)
619    }
620}
621/**Receiver wakeup method
622
623Value on reset: 0*/
624#[cfg_attr(feature = "defmt", derive(defmt::Format))]
625#[derive(Clone, Copy, Debug, PartialEq, Eq)]
626pub enum WAKE {
627    ///0: Idle line
628    Idle = 0,
629    ///1: Address mask
630    Address = 1,
631}
632impl From<WAKE> for bool {
633    #[inline(always)]
634    fn from(variant: WAKE) -> Self {
635        variant as u8 != 0
636    }
637}
638///Field `WAKE` reader - Receiver wakeup method
639pub type WAKE_R = crate::BitReader<WAKE>;
640impl WAKE_R {
641    ///Get enumerated values variant
642    #[inline(always)]
643    pub const fn variant(&self) -> WAKE {
644        match self.bits {
645            false => WAKE::Idle,
646            true => WAKE::Address,
647        }
648    }
649    ///Idle line
650    #[inline(always)]
651    pub fn is_idle(&self) -> bool {
652        *self == WAKE::Idle
653    }
654    ///Address mask
655    #[inline(always)]
656    pub fn is_address(&self) -> bool {
657        *self == WAKE::Address
658    }
659}
660///Field `WAKE` writer - Receiver wakeup method
661pub type WAKE_W<'a, REG> = crate::BitWriter<'a, REG, WAKE>;
662impl<'a, REG> WAKE_W<'a, REG>
663where
664    REG: crate::Writable + crate::RegisterSpec,
665{
666    ///Idle line
667    #[inline(always)]
668    pub fn idle(self) -> &'a mut crate::W<REG> {
669        self.variant(WAKE::Idle)
670    }
671    ///Address mask
672    #[inline(always)]
673    pub fn address(self) -> &'a mut crate::W<REG> {
674        self.variant(WAKE::Address)
675    }
676}
677/**Word length
678
679Value on reset: 0*/
680#[cfg_attr(feature = "defmt", derive(defmt::Format))]
681#[derive(Clone, Copy, Debug, PartialEq, Eq)]
682pub enum M0 {
683    ///0: 1 start bit, 8 data bits, n stop bits
684    Bit8 = 0,
685    ///1: 1 start bit, 9 data bits, n stop bits
686    Bit9 = 1,
687}
688impl From<M0> for bool {
689    #[inline(always)]
690    fn from(variant: M0) -> Self {
691        variant as u8 != 0
692    }
693}
694///Field `M0` reader - Word length
695pub type M0_R = crate::BitReader<M0>;
696impl M0_R {
697    ///Get enumerated values variant
698    #[inline(always)]
699    pub const fn variant(&self) -> M0 {
700        match self.bits {
701            false => M0::Bit8,
702            true => M0::Bit9,
703        }
704    }
705    ///1 start bit, 8 data bits, n stop bits
706    #[inline(always)]
707    pub fn is_bit8(&self) -> bool {
708        *self == M0::Bit8
709    }
710    ///1 start bit, 9 data bits, n stop bits
711    #[inline(always)]
712    pub fn is_bit9(&self) -> bool {
713        *self == M0::Bit9
714    }
715}
716///Field `M0` writer - Word length
717pub type M0_W<'a, REG> = crate::BitWriter<'a, REG, M0>;
718impl<'a, REG> M0_W<'a, REG>
719where
720    REG: crate::Writable + crate::RegisterSpec,
721{
722    ///1 start bit, 8 data bits, n stop bits
723    #[inline(always)]
724    pub fn bit8(self) -> &'a mut crate::W<REG> {
725        self.variant(M0::Bit8)
726    }
727    ///1 start bit, 9 data bits, n stop bits
728    #[inline(always)]
729    pub fn bit9(self) -> &'a mut crate::W<REG> {
730        self.variant(M0::Bit9)
731    }
732}
733/**Mute mode enable
734
735Value on reset: 0*/
736#[cfg_attr(feature = "defmt", derive(defmt::Format))]
737#[derive(Clone, Copy, Debug, PartialEq, Eq)]
738pub enum MME {
739    ///0: Receiver in active mode permanently
740    Disabled = 0,
741    ///1: Receiver can switch between mute mode and active mode
742    Enabled = 1,
743}
744impl From<MME> for bool {
745    #[inline(always)]
746    fn from(variant: MME) -> Self {
747        variant as u8 != 0
748    }
749}
750///Field `MME` reader - Mute mode enable
751pub type MME_R = crate::BitReader<MME>;
752impl MME_R {
753    ///Get enumerated values variant
754    #[inline(always)]
755    pub const fn variant(&self) -> MME {
756        match self.bits {
757            false => MME::Disabled,
758            true => MME::Enabled,
759        }
760    }
761    ///Receiver in active mode permanently
762    #[inline(always)]
763    pub fn is_disabled(&self) -> bool {
764        *self == MME::Disabled
765    }
766    ///Receiver can switch between mute mode and active mode
767    #[inline(always)]
768    pub fn is_enabled(&self) -> bool {
769        *self == MME::Enabled
770    }
771}
772///Field `MME` writer - Mute mode enable
773pub type MME_W<'a, REG> = crate::BitWriter<'a, REG, MME>;
774impl<'a, REG> MME_W<'a, REG>
775where
776    REG: crate::Writable + crate::RegisterSpec,
777{
778    ///Receiver in active mode permanently
779    #[inline(always)]
780    pub fn disabled(self) -> &'a mut crate::W<REG> {
781        self.variant(MME::Disabled)
782    }
783    ///Receiver can switch between mute mode and active mode
784    #[inline(always)]
785    pub fn enabled(self) -> &'a mut crate::W<REG> {
786        self.variant(MME::Enabled)
787    }
788}
789/**Character match interrupt enable
790
791Value on reset: 0*/
792#[cfg_attr(feature = "defmt", derive(defmt::Format))]
793#[derive(Clone, Copy, Debug, PartialEq, Eq)]
794pub enum CMIE {
795    ///0: Interrupt is disabled
796    Disabled = 0,
797    ///1: Interrupt is generated when the CMF bit is set in the ISR register
798    Enabled = 1,
799}
800impl From<CMIE> for bool {
801    #[inline(always)]
802    fn from(variant: CMIE) -> Self {
803        variant as u8 != 0
804    }
805}
806///Field `CMIE` reader - Character match interrupt enable
807pub type CMIE_R = crate::BitReader<CMIE>;
808impl CMIE_R {
809    ///Get enumerated values variant
810    #[inline(always)]
811    pub const fn variant(&self) -> CMIE {
812        match self.bits {
813            false => CMIE::Disabled,
814            true => CMIE::Enabled,
815        }
816    }
817    ///Interrupt is disabled
818    #[inline(always)]
819    pub fn is_disabled(&self) -> bool {
820        *self == CMIE::Disabled
821    }
822    ///Interrupt is generated when the CMF bit is set in the ISR register
823    #[inline(always)]
824    pub fn is_enabled(&self) -> bool {
825        *self == CMIE::Enabled
826    }
827}
828///Field `CMIE` writer - Character match interrupt enable
829pub type CMIE_W<'a, REG> = crate::BitWriter<'a, REG, CMIE>;
830impl<'a, REG> CMIE_W<'a, REG>
831where
832    REG: crate::Writable + crate::RegisterSpec,
833{
834    ///Interrupt is disabled
835    #[inline(always)]
836    pub fn disabled(self) -> &'a mut crate::W<REG> {
837        self.variant(CMIE::Disabled)
838    }
839    ///Interrupt is generated when the CMF bit is set in the ISR register
840    #[inline(always)]
841    pub fn enabled(self) -> &'a mut crate::W<REG> {
842        self.variant(CMIE::Enabled)
843    }
844}
845/**Oversampling mode
846
847Value on reset: 0*/
848#[cfg_attr(feature = "defmt", derive(defmt::Format))]
849#[derive(Clone, Copy, Debug, PartialEq, Eq)]
850pub enum OVER8 {
851    ///0: Oversampling by 16
852    Oversampling16 = 0,
853    ///1: Oversampling by 8
854    Oversampling8 = 1,
855}
856impl From<OVER8> for bool {
857    #[inline(always)]
858    fn from(variant: OVER8) -> Self {
859        variant as u8 != 0
860    }
861}
862///Field `OVER8` reader - Oversampling mode
863pub type OVER8_R = crate::BitReader<OVER8>;
864impl OVER8_R {
865    ///Get enumerated values variant
866    #[inline(always)]
867    pub const fn variant(&self) -> OVER8 {
868        match self.bits {
869            false => OVER8::Oversampling16,
870            true => OVER8::Oversampling8,
871        }
872    }
873    ///Oversampling by 16
874    #[inline(always)]
875    pub fn is_oversampling16(&self) -> bool {
876        *self == OVER8::Oversampling16
877    }
878    ///Oversampling by 8
879    #[inline(always)]
880    pub fn is_oversampling8(&self) -> bool {
881        *self == OVER8::Oversampling8
882    }
883}
884///Field `OVER8` writer - Oversampling mode
885pub type OVER8_W<'a, REG> = crate::BitWriter<'a, REG, OVER8>;
886impl<'a, REG> OVER8_W<'a, REG>
887where
888    REG: crate::Writable + crate::RegisterSpec,
889{
890    ///Oversampling by 16
891    #[inline(always)]
892    pub fn oversampling16(self) -> &'a mut crate::W<REG> {
893        self.variant(OVER8::Oversampling16)
894    }
895    ///Oversampling by 8
896    #[inline(always)]
897    pub fn oversampling8(self) -> &'a mut crate::W<REG> {
898        self.variant(OVER8::Oversampling8)
899    }
900}
901///Field `DEDT` reader - Driver Enable de-assertion time
902pub type DEDT_R = crate::FieldReader;
903///Field `DEDT` writer - Driver Enable de-assertion time
904pub type DEDT_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
905///Field `DEAT` reader - Driver Enable assertion time
906pub type DEAT_R = crate::FieldReader;
907///Field `DEAT` writer - Driver Enable assertion time
908pub type DEAT_W<'a, REG> = crate::FieldWriter<'a, REG, 5, u8, crate::Safe>;
909/**Receiver timeout interrupt enable
910
911Value on reset: 0*/
912#[cfg_attr(feature = "defmt", derive(defmt::Format))]
913#[derive(Clone, Copy, Debug, PartialEq, Eq)]
914pub enum RTOIE {
915    ///0: Interrupt is inhibited
916    Disabled = 0,
917    ///1: An USART interrupt is generated when the RTOF bit is set in the ISR register
918    Enabled = 1,
919}
920impl From<RTOIE> for bool {
921    #[inline(always)]
922    fn from(variant: RTOIE) -> Self {
923        variant as u8 != 0
924    }
925}
926///Field `RTOIE` reader - Receiver timeout interrupt enable
927pub type RTOIE_R = crate::BitReader<RTOIE>;
928impl RTOIE_R {
929    ///Get enumerated values variant
930    #[inline(always)]
931    pub const fn variant(&self) -> RTOIE {
932        match self.bits {
933            false => RTOIE::Disabled,
934            true => RTOIE::Enabled,
935        }
936    }
937    ///Interrupt is inhibited
938    #[inline(always)]
939    pub fn is_disabled(&self) -> bool {
940        *self == RTOIE::Disabled
941    }
942    ///An USART interrupt is generated when the RTOF bit is set in the ISR register
943    #[inline(always)]
944    pub fn is_enabled(&self) -> bool {
945        *self == RTOIE::Enabled
946    }
947}
948///Field `RTOIE` writer - Receiver timeout interrupt enable
949pub type RTOIE_W<'a, REG> = crate::BitWriter<'a, REG, RTOIE>;
950impl<'a, REG> RTOIE_W<'a, REG>
951where
952    REG: crate::Writable + crate::RegisterSpec,
953{
954    ///Interrupt is inhibited
955    #[inline(always)]
956    pub fn disabled(self) -> &'a mut crate::W<REG> {
957        self.variant(RTOIE::Disabled)
958    }
959    ///An USART interrupt is generated when the RTOF bit is set in the ISR register
960    #[inline(always)]
961    pub fn enabled(self) -> &'a mut crate::W<REG> {
962        self.variant(RTOIE::Enabled)
963    }
964}
965/**End of Block interrupt enable
966
967Value on reset: 0*/
968#[cfg_attr(feature = "defmt", derive(defmt::Format))]
969#[derive(Clone, Copy, Debug, PartialEq, Eq)]
970pub enum EOBIE {
971    ///0: Interrupt is inhibited
972    Disabled = 0,
973    ///1: A USART interrupt is generated when the EOBF flag is set in the ISR register
974    Enabled = 1,
975}
976impl From<EOBIE> for bool {
977    #[inline(always)]
978    fn from(variant: EOBIE) -> Self {
979        variant as u8 != 0
980    }
981}
982///Field `EOBIE` reader - End of Block interrupt enable
983pub type EOBIE_R = crate::BitReader<EOBIE>;
984impl EOBIE_R {
985    ///Get enumerated values variant
986    #[inline(always)]
987    pub const fn variant(&self) -> EOBIE {
988        match self.bits {
989            false => EOBIE::Disabled,
990            true => EOBIE::Enabled,
991        }
992    }
993    ///Interrupt is inhibited
994    #[inline(always)]
995    pub fn is_disabled(&self) -> bool {
996        *self == EOBIE::Disabled
997    }
998    ///A USART interrupt is generated when the EOBF flag is set in the ISR register
999    #[inline(always)]
1000    pub fn is_enabled(&self) -> bool {
1001        *self == EOBIE::Enabled
1002    }
1003}
1004///Field `EOBIE` writer - End of Block interrupt enable
1005pub type EOBIE_W<'a, REG> = crate::BitWriter<'a, REG, EOBIE>;
1006impl<'a, REG> EOBIE_W<'a, REG>
1007where
1008    REG: crate::Writable + crate::RegisterSpec,
1009{
1010    ///Interrupt is inhibited
1011    #[inline(always)]
1012    pub fn disabled(self) -> &'a mut crate::W<REG> {
1013        self.variant(EOBIE::Disabled)
1014    }
1015    ///A USART interrupt is generated when the EOBF flag is set in the ISR register
1016    #[inline(always)]
1017    pub fn enabled(self) -> &'a mut crate::W<REG> {
1018        self.variant(EOBIE::Enabled)
1019    }
1020}
1021/**M1
1022
1023Value on reset: 0*/
1024#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1025#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1026pub enum M1 {
1027    ///0: Use M0 to set the data bits
1028    M0 = 0,
1029    ///1: 1 start bit, 7 data bits, n stop bits
1030    Bit7 = 1,
1031}
1032impl From<M1> for bool {
1033    #[inline(always)]
1034    fn from(variant: M1) -> Self {
1035        variant as u8 != 0
1036    }
1037}
1038///Field `M1` reader - M1
1039pub type M1_R = crate::BitReader<M1>;
1040impl M1_R {
1041    ///Get enumerated values variant
1042    #[inline(always)]
1043    pub const fn variant(&self) -> M1 {
1044        match self.bits {
1045            false => M1::M0,
1046            true => M1::Bit7,
1047        }
1048    }
1049    ///Use M0 to set the data bits
1050    #[inline(always)]
1051    pub fn is_m0(&self) -> bool {
1052        *self == M1::M0
1053    }
1054    ///1 start bit, 7 data bits, n stop bits
1055    #[inline(always)]
1056    pub fn is_bit7(&self) -> bool {
1057        *self == M1::Bit7
1058    }
1059}
1060///Field `M1` writer - M1
1061pub type M1_W<'a, REG> = crate::BitWriter<'a, REG, M1>;
1062impl<'a, REG> M1_W<'a, REG>
1063where
1064    REG: crate::Writable + crate::RegisterSpec,
1065{
1066    ///Use M0 to set the data bits
1067    #[inline(always)]
1068    pub fn m0(self) -> &'a mut crate::W<REG> {
1069        self.variant(M1::M0)
1070    }
1071    ///1 start bit, 7 data bits, n stop bits
1072    #[inline(always)]
1073    pub fn bit7(self) -> &'a mut crate::W<REG> {
1074        self.variant(M1::Bit7)
1075    }
1076}
1077/**FIFOEN
1078
1079Value on reset: 0*/
1080#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1081#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1082pub enum FIFOEN {
1083    ///0: FIFO mode is disabled
1084    Disabled = 0,
1085    ///1: FIFO mode is enabled
1086    Enabled = 1,
1087}
1088impl From<FIFOEN> for bool {
1089    #[inline(always)]
1090    fn from(variant: FIFOEN) -> Self {
1091        variant as u8 != 0
1092    }
1093}
1094///Field `FIFOEN` reader - FIFOEN
1095pub type FIFOEN_R = crate::BitReader<FIFOEN>;
1096impl FIFOEN_R {
1097    ///Get enumerated values variant
1098    #[inline(always)]
1099    pub const fn variant(&self) -> FIFOEN {
1100        match self.bits {
1101            false => FIFOEN::Disabled,
1102            true => FIFOEN::Enabled,
1103        }
1104    }
1105    ///FIFO mode is disabled
1106    #[inline(always)]
1107    pub fn is_disabled(&self) -> bool {
1108        *self == FIFOEN::Disabled
1109    }
1110    ///FIFO mode is enabled
1111    #[inline(always)]
1112    pub fn is_enabled(&self) -> bool {
1113        *self == FIFOEN::Enabled
1114    }
1115}
1116///Field `FIFOEN` writer - FIFOEN
1117pub type FIFOEN_W<'a, REG> = crate::BitWriter<'a, REG, FIFOEN>;
1118impl<'a, REG> FIFOEN_W<'a, REG>
1119where
1120    REG: crate::Writable + crate::RegisterSpec,
1121{
1122    ///FIFO mode is disabled
1123    #[inline(always)]
1124    pub fn disabled(self) -> &'a mut crate::W<REG> {
1125        self.variant(FIFOEN::Disabled)
1126    }
1127    ///FIFO mode is enabled
1128    #[inline(always)]
1129    pub fn enabled(self) -> &'a mut crate::W<REG> {
1130        self.variant(FIFOEN::Enabled)
1131    }
1132}
1133/**TXFEIE
1134
1135Value on reset: 0*/
1136#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1137#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1138pub enum TXFEIE {
1139    ///0: Interrupt inhibited
1140    Disabled = 0,
1141    ///1: USART interrupt generated when TXFE = 1 in the USART_ISR register
1142    Enabled = 1,
1143}
1144impl From<TXFEIE> for bool {
1145    #[inline(always)]
1146    fn from(variant: TXFEIE) -> Self {
1147        variant as u8 != 0
1148    }
1149}
1150///Field `TXFEIE` reader - TXFEIE
1151pub type TXFEIE_R = crate::BitReader<TXFEIE>;
1152impl TXFEIE_R {
1153    ///Get enumerated values variant
1154    #[inline(always)]
1155    pub const fn variant(&self) -> TXFEIE {
1156        match self.bits {
1157            false => TXFEIE::Disabled,
1158            true => TXFEIE::Enabled,
1159        }
1160    }
1161    ///Interrupt inhibited
1162    #[inline(always)]
1163    pub fn is_disabled(&self) -> bool {
1164        *self == TXFEIE::Disabled
1165    }
1166    ///USART interrupt generated when TXFE = 1 in the USART_ISR register
1167    #[inline(always)]
1168    pub fn is_enabled(&self) -> bool {
1169        *self == TXFEIE::Enabled
1170    }
1171}
1172///Field `TXFEIE` writer - TXFEIE
1173pub type TXFEIE_W<'a, REG> = crate::BitWriter<'a, REG, TXFEIE>;
1174impl<'a, REG> TXFEIE_W<'a, REG>
1175where
1176    REG: crate::Writable + crate::RegisterSpec,
1177{
1178    ///Interrupt inhibited
1179    #[inline(always)]
1180    pub fn disabled(self) -> &'a mut crate::W<REG> {
1181        self.variant(TXFEIE::Disabled)
1182    }
1183    ///USART interrupt generated when TXFE = 1 in the USART_ISR register
1184    #[inline(always)]
1185    pub fn enabled(self) -> &'a mut crate::W<REG> {
1186        self.variant(TXFEIE::Enabled)
1187    }
1188}
1189/**RXFFIE
1190
1191Value on reset: 0*/
1192#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1194pub enum RXFFIE {
1195    ///0: Interrupt inhibited
1196    Disabled = 0,
1197    ///1: USART interrupt generated when RXFF = 1 in the USART_ISR register
1198    Enabled = 1,
1199}
1200impl From<RXFFIE> for bool {
1201    #[inline(always)]
1202    fn from(variant: RXFFIE) -> Self {
1203        variant as u8 != 0
1204    }
1205}
1206///Field `RXFFIE` reader - RXFFIE
1207pub type RXFFIE_R = crate::BitReader<RXFFIE>;
1208impl RXFFIE_R {
1209    ///Get enumerated values variant
1210    #[inline(always)]
1211    pub const fn variant(&self) -> RXFFIE {
1212        match self.bits {
1213            false => RXFFIE::Disabled,
1214            true => RXFFIE::Enabled,
1215        }
1216    }
1217    ///Interrupt inhibited
1218    #[inline(always)]
1219    pub fn is_disabled(&self) -> bool {
1220        *self == RXFFIE::Disabled
1221    }
1222    ///USART interrupt generated when RXFF = 1 in the USART_ISR register
1223    #[inline(always)]
1224    pub fn is_enabled(&self) -> bool {
1225        *self == RXFFIE::Enabled
1226    }
1227}
1228///Field `RXFFIE` writer - RXFFIE
1229pub type RXFFIE_W<'a, REG> = crate::BitWriter<'a, REG, RXFFIE>;
1230impl<'a, REG> RXFFIE_W<'a, REG>
1231where
1232    REG: crate::Writable + crate::RegisterSpec,
1233{
1234    ///Interrupt inhibited
1235    #[inline(always)]
1236    pub fn disabled(self) -> &'a mut crate::W<REG> {
1237        self.variant(RXFFIE::Disabled)
1238    }
1239    ///USART interrupt generated when RXFF = 1 in the USART_ISR register
1240    #[inline(always)]
1241    pub fn enabled(self) -> &'a mut crate::W<REG> {
1242        self.variant(RXFFIE::Enabled)
1243    }
1244}
1245impl R {
1246    ///Bit 0 - USART enable
1247    #[inline(always)]
1248    pub fn ue(&self) -> UE_R {
1249        UE_R::new((self.bits & 1) != 0)
1250    }
1251    ///Bit 1 - USART enable in Stop mode
1252    #[inline(always)]
1253    pub fn uesm(&self) -> UESM_R {
1254        UESM_R::new(((self.bits >> 1) & 1) != 0)
1255    }
1256    ///Bit 2 - Receiver enable
1257    #[inline(always)]
1258    pub fn re(&self) -> RE_R {
1259        RE_R::new(((self.bits >> 2) & 1) != 0)
1260    }
1261    ///Bit 3 - Transmitter enable
1262    #[inline(always)]
1263    pub fn te(&self) -> TE_R {
1264        TE_R::new(((self.bits >> 3) & 1) != 0)
1265    }
1266    ///Bit 4 - IDLE interrupt enable
1267    #[inline(always)]
1268    pub fn idleie(&self) -> IDLEIE_R {
1269        IDLEIE_R::new(((self.bits >> 4) & 1) != 0)
1270    }
1271    ///Bit 5 - RXNE interrupt enable
1272    #[inline(always)]
1273    pub fn rxneie(&self) -> RXNEIE_R {
1274        RXNEIE_R::new(((self.bits >> 5) & 1) != 0)
1275    }
1276    ///Bit 6 - Transmission complete interrupt enable
1277    #[inline(always)]
1278    pub fn tcie(&self) -> TCIE_R {
1279        TCIE_R::new(((self.bits >> 6) & 1) != 0)
1280    }
1281    ///Bit 7 - interrupt enable
1282    #[inline(always)]
1283    pub fn txeie(&self) -> TXEIE_R {
1284        TXEIE_R::new(((self.bits >> 7) & 1) != 0)
1285    }
1286    ///Bit 8 - PE interrupt enable
1287    #[inline(always)]
1288    pub fn peie(&self) -> PEIE_R {
1289        PEIE_R::new(((self.bits >> 8) & 1) != 0)
1290    }
1291    ///Bit 9 - Parity selection
1292    #[inline(always)]
1293    pub fn ps(&self) -> PS_R {
1294        PS_R::new(((self.bits >> 9) & 1) != 0)
1295    }
1296    ///Bit 10 - Parity control enable
1297    #[inline(always)]
1298    pub fn pce(&self) -> PCE_R {
1299        PCE_R::new(((self.bits >> 10) & 1) != 0)
1300    }
1301    ///Bit 11 - Receiver wakeup method
1302    #[inline(always)]
1303    pub fn wake(&self) -> WAKE_R {
1304        WAKE_R::new(((self.bits >> 11) & 1) != 0)
1305    }
1306    ///Bit 12 - Word length
1307    #[inline(always)]
1308    pub fn m0(&self) -> M0_R {
1309        M0_R::new(((self.bits >> 12) & 1) != 0)
1310    }
1311    ///Bit 13 - Mute mode enable
1312    #[inline(always)]
1313    pub fn mme(&self) -> MME_R {
1314        MME_R::new(((self.bits >> 13) & 1) != 0)
1315    }
1316    ///Bit 14 - Character match interrupt enable
1317    #[inline(always)]
1318    pub fn cmie(&self) -> CMIE_R {
1319        CMIE_R::new(((self.bits >> 14) & 1) != 0)
1320    }
1321    ///Bit 15 - Oversampling mode
1322    #[inline(always)]
1323    pub fn over8(&self) -> OVER8_R {
1324        OVER8_R::new(((self.bits >> 15) & 1) != 0)
1325    }
1326    ///Bits 16:20 - Driver Enable de-assertion time
1327    #[inline(always)]
1328    pub fn dedt(&self) -> DEDT_R {
1329        DEDT_R::new(((self.bits >> 16) & 0x1f) as u8)
1330    }
1331    ///Bits 21:25 - Driver Enable assertion time
1332    #[inline(always)]
1333    pub fn deat(&self) -> DEAT_R {
1334        DEAT_R::new(((self.bits >> 21) & 0x1f) as u8)
1335    }
1336    ///Bit 26 - Receiver timeout interrupt enable
1337    #[inline(always)]
1338    pub fn rtoie(&self) -> RTOIE_R {
1339        RTOIE_R::new(((self.bits >> 26) & 1) != 0)
1340    }
1341    ///Bit 27 - End of Block interrupt enable
1342    #[inline(always)]
1343    pub fn eobie(&self) -> EOBIE_R {
1344        EOBIE_R::new(((self.bits >> 27) & 1) != 0)
1345    }
1346    ///Bit 28 - M1
1347    #[inline(always)]
1348    pub fn m1(&self) -> M1_R {
1349        M1_R::new(((self.bits >> 28) & 1) != 0)
1350    }
1351    ///Bit 29 - FIFOEN
1352    #[inline(always)]
1353    pub fn fifoen(&self) -> FIFOEN_R {
1354        FIFOEN_R::new(((self.bits >> 29) & 1) != 0)
1355    }
1356    ///Bit 30 - TXFEIE
1357    #[inline(always)]
1358    pub fn txfeie(&self) -> TXFEIE_R {
1359        TXFEIE_R::new(((self.bits >> 30) & 1) != 0)
1360    }
1361    ///Bit 31 - RXFFIE
1362    #[inline(always)]
1363    pub fn rxffie(&self) -> RXFFIE_R {
1364        RXFFIE_R::new(((self.bits >> 31) & 1) != 0)
1365    }
1366}
1367impl core::fmt::Debug for R {
1368    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1369        f.debug_struct("CR1")
1370            .field("rxffie", &self.rxffie())
1371            .field("txfeie", &self.txfeie())
1372            .field("fifoen", &self.fifoen())
1373            .field("m1", &self.m1())
1374            .field("eobie", &self.eobie())
1375            .field("rtoie", &self.rtoie())
1376            .field("deat", &self.deat())
1377            .field("dedt", &self.dedt())
1378            .field("over8", &self.over8())
1379            .field("cmie", &self.cmie())
1380            .field("mme", &self.mme())
1381            .field("m0", &self.m0())
1382            .field("wake", &self.wake())
1383            .field("pce", &self.pce())
1384            .field("ps", &self.ps())
1385            .field("peie", &self.peie())
1386            .field("txeie", &self.txeie())
1387            .field("tcie", &self.tcie())
1388            .field("rxneie", &self.rxneie())
1389            .field("idleie", &self.idleie())
1390            .field("te", &self.te())
1391            .field("re", &self.re())
1392            .field("uesm", &self.uesm())
1393            .field("ue", &self.ue())
1394            .finish()
1395    }
1396}
1397impl W {
1398    ///Bit 0 - USART enable
1399    #[inline(always)]
1400    pub fn ue(&mut self) -> UE_W<CR1rs> {
1401        UE_W::new(self, 0)
1402    }
1403    ///Bit 1 - USART enable in Stop mode
1404    #[inline(always)]
1405    pub fn uesm(&mut self) -> UESM_W<CR1rs> {
1406        UESM_W::new(self, 1)
1407    }
1408    ///Bit 2 - Receiver enable
1409    #[inline(always)]
1410    pub fn re(&mut self) -> RE_W<CR1rs> {
1411        RE_W::new(self, 2)
1412    }
1413    ///Bit 3 - Transmitter enable
1414    #[inline(always)]
1415    pub fn te(&mut self) -> TE_W<CR1rs> {
1416        TE_W::new(self, 3)
1417    }
1418    ///Bit 4 - IDLE interrupt enable
1419    #[inline(always)]
1420    pub fn idleie(&mut self) -> IDLEIE_W<CR1rs> {
1421        IDLEIE_W::new(self, 4)
1422    }
1423    ///Bit 5 - RXNE interrupt enable
1424    #[inline(always)]
1425    pub fn rxneie(&mut self) -> RXNEIE_W<CR1rs> {
1426        RXNEIE_W::new(self, 5)
1427    }
1428    ///Bit 6 - Transmission complete interrupt enable
1429    #[inline(always)]
1430    pub fn tcie(&mut self) -> TCIE_W<CR1rs> {
1431        TCIE_W::new(self, 6)
1432    }
1433    ///Bit 7 - interrupt enable
1434    #[inline(always)]
1435    pub fn txeie(&mut self) -> TXEIE_W<CR1rs> {
1436        TXEIE_W::new(self, 7)
1437    }
1438    ///Bit 8 - PE interrupt enable
1439    #[inline(always)]
1440    pub fn peie(&mut self) -> PEIE_W<CR1rs> {
1441        PEIE_W::new(self, 8)
1442    }
1443    ///Bit 9 - Parity selection
1444    #[inline(always)]
1445    pub fn ps(&mut self) -> PS_W<CR1rs> {
1446        PS_W::new(self, 9)
1447    }
1448    ///Bit 10 - Parity control enable
1449    #[inline(always)]
1450    pub fn pce(&mut self) -> PCE_W<CR1rs> {
1451        PCE_W::new(self, 10)
1452    }
1453    ///Bit 11 - Receiver wakeup method
1454    #[inline(always)]
1455    pub fn wake(&mut self) -> WAKE_W<CR1rs> {
1456        WAKE_W::new(self, 11)
1457    }
1458    ///Bit 12 - Word length
1459    #[inline(always)]
1460    pub fn m0(&mut self) -> M0_W<CR1rs> {
1461        M0_W::new(self, 12)
1462    }
1463    ///Bit 13 - Mute mode enable
1464    #[inline(always)]
1465    pub fn mme(&mut self) -> MME_W<CR1rs> {
1466        MME_W::new(self, 13)
1467    }
1468    ///Bit 14 - Character match interrupt enable
1469    #[inline(always)]
1470    pub fn cmie(&mut self) -> CMIE_W<CR1rs> {
1471        CMIE_W::new(self, 14)
1472    }
1473    ///Bit 15 - Oversampling mode
1474    #[inline(always)]
1475    pub fn over8(&mut self) -> OVER8_W<CR1rs> {
1476        OVER8_W::new(self, 15)
1477    }
1478    ///Bits 16:20 - Driver Enable de-assertion time
1479    #[inline(always)]
1480    pub fn dedt(&mut self) -> DEDT_W<CR1rs> {
1481        DEDT_W::new(self, 16)
1482    }
1483    ///Bits 21:25 - Driver Enable assertion time
1484    #[inline(always)]
1485    pub fn deat(&mut self) -> DEAT_W<CR1rs> {
1486        DEAT_W::new(self, 21)
1487    }
1488    ///Bit 26 - Receiver timeout interrupt enable
1489    #[inline(always)]
1490    pub fn rtoie(&mut self) -> RTOIE_W<CR1rs> {
1491        RTOIE_W::new(self, 26)
1492    }
1493    ///Bit 27 - End of Block interrupt enable
1494    #[inline(always)]
1495    pub fn eobie(&mut self) -> EOBIE_W<CR1rs> {
1496        EOBIE_W::new(self, 27)
1497    }
1498    ///Bit 28 - M1
1499    #[inline(always)]
1500    pub fn m1(&mut self) -> M1_W<CR1rs> {
1501        M1_W::new(self, 28)
1502    }
1503    ///Bit 29 - FIFOEN
1504    #[inline(always)]
1505    pub fn fifoen(&mut self) -> FIFOEN_W<CR1rs> {
1506        FIFOEN_W::new(self, 29)
1507    }
1508    ///Bit 30 - TXFEIE
1509    #[inline(always)]
1510    pub fn txfeie(&mut self) -> TXFEIE_W<CR1rs> {
1511        TXFEIE_W::new(self, 30)
1512    }
1513    ///Bit 31 - RXFFIE
1514    #[inline(always)]
1515    pub fn rxffie(&mut self) -> RXFFIE_W<CR1rs> {
1516        RXFFIE_W::new(self, 31)
1517    }
1518}
1519/**Control register 1
1520
1521You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1522
1523See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#UART4:CR1)*/
1524pub struct CR1rs;
1525impl crate::RegisterSpec for CR1rs {
1526    type Ux = u32;
1527}
1528///`read()` method returns [`cr1::R`](R) reader structure
1529impl crate::Readable for CR1rs {}
1530///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
1531impl crate::Writable for CR1rs {
1532    type Safety = crate::Unsafe;
1533    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1534    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1535}
1536///`reset()` method sets CR1 to value 0
1537impl crate::Resettable for CR1rs {
1538    const RESET_VALUE: u32 = 0;
1539}
stm32g4_staging/stm32g474/uart4/cr1.rs

stm32g4_staging/stm32g474/uart4/
cr1.rs
