stm32g4_staging/stm32g474/lpuart1/
presc.rs

1///Register `PRESC` reader
2pub type R = crate::R<PRESCrs>;
3///Register `PRESC` writer
4pub type W = crate::W<PRESCrs>;
5/**PRESCALER
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum PRESCALER {
12    ///0: /1
13    Div1 = 0,
14    ///1: /2
15    Div2 = 1,
16    ///2: /4
17    Div4 = 2,
18    ///3: /6
19    Div6 = 3,
20    ///4: /8
21    Div8 = 4,
22    ///5: /10
23    Div10 = 5,
24    ///6: /12
25    Div12 = 6,
26    ///7: /16
27    Div16 = 7,
28    ///8: /32
29    Div32 = 8,
30    ///9: /64
31    Div64 = 9,
32    ///10: /128
33    Div128 = 10,
34    ///11: /256
35    Div256 = 11,
36}
37impl From<PRESCALER> for u8 {
38    #[inline(always)]
39    fn from(variant: PRESCALER) -> Self {
40        variant as _
41    }
42}
43impl crate::FieldSpec for PRESCALER {
44    type Ux = u8;
45}
46impl crate::IsEnum for PRESCALER {}
47///Field `PRESCALER` reader - PRESCALER
48pub type PRESCALER_R = crate::FieldReader<PRESCALER>;
49impl PRESCALER_R {
50    ///Get enumerated values variant
51    #[inline(always)]
52    pub const fn variant(&self) -> Option<PRESCALER> {
53        match self.bits {
54            0 => Some(PRESCALER::Div1),
55            1 => Some(PRESCALER::Div2),
56            2 => Some(PRESCALER::Div4),
57            3 => Some(PRESCALER::Div6),
58            4 => Some(PRESCALER::Div8),
59            5 => Some(PRESCALER::Div10),
60            6 => Some(PRESCALER::Div12),
61            7 => Some(PRESCALER::Div16),
62            8 => Some(PRESCALER::Div32),
63            9 => Some(PRESCALER::Div64),
64            10 => Some(PRESCALER::Div128),
65            11 => Some(PRESCALER::Div256),
66            _ => None,
67        }
68    }
69    #[doc = "/1"]
70    #[inline(always)]
71    pub fn is_div1(&self) -> bool {
72        *self == PRESCALER::Div1
73    }
74    #[doc = "/2"]
75    #[inline(always)]
76    pub fn is_div2(&self) -> bool {
77        *self == PRESCALER::Div2
78    }
79    #[doc = "/4"]
80    #[inline(always)]
81    pub fn is_div4(&self) -> bool {
82        *self == PRESCALER::Div4
83    }
84    #[doc = "/6"]
85    #[inline(always)]
86    pub fn is_div6(&self) -> bool {
87        *self == PRESCALER::Div6
88    }
89    #[doc = "/8"]
90    #[inline(always)]
91    pub fn is_div8(&self) -> bool {
92        *self == PRESCALER::Div8
93    }
94    #[doc = "/10"]
95    #[inline(always)]
96    pub fn is_div10(&self) -> bool {
97        *self == PRESCALER::Div10
98    }
99    #[doc = "/12"]
100    #[inline(always)]
101    pub fn is_div12(&self) -> bool {
102        *self == PRESCALER::Div12
103    }
104    #[doc = "/16"]
105    #[inline(always)]
106    pub fn is_div16(&self) -> bool {
107        *self == PRESCALER::Div16
108    }
109    #[doc = "/32"]
110    #[inline(always)]
111    pub fn is_div32(&self) -> bool {
112        *self == PRESCALER::Div32
113    }
114    #[doc = "/64"]
115    #[inline(always)]
116    pub fn is_div64(&self) -> bool {
117        *self == PRESCALER::Div64
118    }
119    #[doc = "/128"]
120    #[inline(always)]
121    pub fn is_div128(&self) -> bool {
122        *self == PRESCALER::Div128
123    }
124    #[doc = "/256"]
125    #[inline(always)]
126    pub fn is_div256(&self) -> bool {
127        *self == PRESCALER::Div256
128    }
129}
130///Field `PRESCALER` writer - PRESCALER
131pub type PRESCALER_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PRESCALER>;
132impl<'a, REG> PRESCALER_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135    REG::Ux: From<u8>,
136{
137    #[doc = "/1"]
138    #[inline(always)]
139    pub fn div1(self) -> &'a mut crate::W<REG> {
140        self.variant(PRESCALER::Div1)
141    }
142    #[doc = "/2"]
143    #[inline(always)]
144    pub fn div2(self) -> &'a mut crate::W<REG> {
145        self.variant(PRESCALER::Div2)
146    }
147    #[doc = "/4"]
148    #[inline(always)]
149    pub fn div4(self) -> &'a mut crate::W<REG> {
150        self.variant(PRESCALER::Div4)
151    }
152    #[doc = "/6"]
153    #[inline(always)]
154    pub fn div6(self) -> &'a mut crate::W<REG> {
155        self.variant(PRESCALER::Div6)
156    }
157    #[doc = "/8"]
158    #[inline(always)]
159    pub fn div8(self) -> &'a mut crate::W<REG> {
160        self.variant(PRESCALER::Div8)
161    }
162    #[doc = "/10"]
163    #[inline(always)]
164    pub fn div10(self) -> &'a mut crate::W<REG> {
165        self.variant(PRESCALER::Div10)
166    }
167    #[doc = "/12"]
168    #[inline(always)]
169    pub fn div12(self) -> &'a mut crate::W<REG> {
170        self.variant(PRESCALER::Div12)
171    }
172    #[doc = "/16"]
173    #[inline(always)]
174    pub fn div16(self) -> &'a mut crate::W<REG> {
175        self.variant(PRESCALER::Div16)
176    }
177    #[doc = "/32"]
178    #[inline(always)]
179    pub fn div32(self) -> &'a mut crate::W<REG> {
180        self.variant(PRESCALER::Div32)
181    }
182    #[doc = "/64"]
183    #[inline(always)]
184    pub fn div64(self) -> &'a mut crate::W<REG> {
185        self.variant(PRESCALER::Div64)
186    }
187    #[doc = "/128"]
188    #[inline(always)]
189    pub fn div128(self) -> &'a mut crate::W<REG> {
190        self.variant(PRESCALER::Div128)
191    }
192    #[doc = "/256"]
193    #[inline(always)]
194    pub fn div256(self) -> &'a mut crate::W<REG> {
195        self.variant(PRESCALER::Div256)
196    }
197}
198impl R {
199    ///Bits 0:3 - PRESCALER
200    #[inline(always)]
201    pub fn prescaler(&self) -> PRESCALER_R {
202        PRESCALER_R::new((self.bits & 0x0f) as u8)
203    }
204}
205impl core::fmt::Debug for R {
206    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
207        f.debug_struct("PRESC").field("prescaler", &self.prescaler()).finish()
208    }
209}
210impl W {
211    ///Bits 0:3 - PRESCALER
212    #[inline(always)]
213    pub fn prescaler(&mut self) -> PRESCALER_W<PRESCrs> {
214        PRESCALER_W::new(self, 0)
215    }
216}
217/**Prescaler register
218
219You can [`read`](crate::Reg::read) this register and get [`presc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`presc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#LPUART1:PRESC)*/
222pub struct PRESCrs;
223impl crate::RegisterSpec for PRESCrs {
224    type Ux = u32;
225}
226///`read()` method returns [`presc::R`](R) reader structure
227impl crate::Readable for PRESCrs {}
228///`write(|w| ..)` method takes [`presc::W`](W) writer structure
229impl crate::Writable for PRESCrs {
230    type Safety = crate::Unsafe;
231    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
232    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
233}
234///`reset()` method sets PRESC to value 0
235impl crate::Resettable for PRESCrs {
236    const RESET_VALUE: u32 = 0;
237}
stm32g4_staging/stm32g474/lpuart1/presc.rs

stm32g4_staging/stm32g474/lpuart1/
presc.rs
