stm32g4_staging/stm32g441/tamp/
scr.rs

1///Register `SCR` reader
2pub type R = crate::R<SCRrs>;
3///Register `SCR` writer
4pub type W = crate::W<SCRrs>;
5///Field `CTAMP1F` reader - CTAMP1F
6pub type CTAMP1F_R = crate::BitReader;
7///Field `CTAMP1F` writer - CTAMP1F
8pub type CTAMP1F_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CTAMP2F` reader - CTAMP2F
10pub type CTAMP2F_R = crate::BitReader;
11///Field `CTAMP2F` writer - CTAMP2F
12pub type CTAMP2F_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CTAMP3F` reader - CTAMP3F
14pub type CTAMP3F_R = crate::BitReader;
15///Field `CTAMP3F` writer - CTAMP3F
16pub type CTAMP3F_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CITAMP3F` reader - CITAMP3F
18pub type CITAMP3F_R = crate::BitReader;
19///Field `CITAMP3F` writer - CITAMP3F
20pub type CITAMP3F_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `CITAMP4F` reader - CITAMP4F
22pub type CITAMP4F_R = crate::BitReader;
23///Field `CITAMP4F` writer - CITAMP4F
24pub type CITAMP4F_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `CITAMP5F` reader - CITAMP5F
26pub type CITAMP5F_R = crate::BitReader;
27///Field `CITAMP5F` writer - CITAMP5F
28pub type CITAMP5F_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `CITAMP6F` reader - CITAMP6F
30pub type CITAMP6F_R = crate::BitReader;
31///Field `CITAMP6F` writer - CITAMP6F
32pub type CITAMP6F_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    ///Bit 0 - CTAMP1F
35    #[inline(always)]
36    pub fn ctamp1f(&self) -> CTAMP1F_R {
37        CTAMP1F_R::new((self.bits & 1) != 0)
38    }
39    ///Bit 1 - CTAMP2F
40    #[inline(always)]
41    pub fn ctamp2f(&self) -> CTAMP2F_R {
42        CTAMP2F_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    ///Bit 2 - CTAMP3F
45    #[inline(always)]
46    pub fn ctamp3f(&self) -> CTAMP3F_R {
47        CTAMP3F_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    ///Bit 18 - CITAMP3F
50    #[inline(always)]
51    pub fn citamp3f(&self) -> CITAMP3F_R {
52        CITAMP3F_R::new(((self.bits >> 18) & 1) != 0)
53    }
54    ///Bit 19 - CITAMP4F
55    #[inline(always)]
56    pub fn citamp4f(&self) -> CITAMP4F_R {
57        CITAMP4F_R::new(((self.bits >> 19) & 1) != 0)
58    }
59    ///Bit 20 - CITAMP5F
60    #[inline(always)]
61    pub fn citamp5f(&self) -> CITAMP5F_R {
62        CITAMP5F_R::new(((self.bits >> 20) & 1) != 0)
63    }
64    ///Bit 21 - CITAMP6F
65    #[inline(always)]
66    pub fn citamp6f(&self) -> CITAMP6F_R {
67        CITAMP6F_R::new(((self.bits >> 21) & 1) != 0)
68    }
69}
70impl core::fmt::Debug for R {
71    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
72        f.debug_struct("SCR")
73            .field("ctamp1f", &self.ctamp1f())
74            .field("ctamp2f", &self.ctamp2f())
75            .field("ctamp3f", &self.ctamp3f())
76            .field("citamp3f", &self.citamp3f())
77            .field("citamp4f", &self.citamp4f())
78            .field("citamp5f", &self.citamp5f())
79            .field("citamp6f", &self.citamp6f())
80            .finish()
81    }
82}
83impl W {
84    ///Bit 0 - CTAMP1F
85    #[inline(always)]
86    pub fn ctamp1f(&mut self) -> CTAMP1F_W<SCRrs> {
87        CTAMP1F_W::new(self, 0)
88    }
89    ///Bit 1 - CTAMP2F
90    #[inline(always)]
91    pub fn ctamp2f(&mut self) -> CTAMP2F_W<SCRrs> {
92        CTAMP2F_W::new(self, 1)
93    }
94    ///Bit 2 - CTAMP3F
95    #[inline(always)]
96    pub fn ctamp3f(&mut self) -> CTAMP3F_W<SCRrs> {
97        CTAMP3F_W::new(self, 2)
98    }
99    ///Bit 18 - CITAMP3F
100    #[inline(always)]
101    pub fn citamp3f(&mut self) -> CITAMP3F_W<SCRrs> {
102        CITAMP3F_W::new(self, 18)
103    }
104    ///Bit 19 - CITAMP4F
105    #[inline(always)]
106    pub fn citamp4f(&mut self) -> CITAMP4F_W<SCRrs> {
107        CITAMP4F_W::new(self, 19)
108    }
109    ///Bit 20 - CITAMP5F
110    #[inline(always)]
111    pub fn citamp5f(&mut self) -> CITAMP5F_W<SCRrs> {
112        CITAMP5F_W::new(self, 20)
113    }
114    ///Bit 21 - CITAMP6F
115    #[inline(always)]
116    pub fn citamp6f(&mut self) -> CITAMP6F_W<SCRrs> {
117        CITAMP6F_W::new(self, 21)
118    }
119}
120/**TAMP status clear register
121
122You can [`read`](crate::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#TAMP:SCR)*/
125pub struct SCRrs;
126impl crate::RegisterSpec for SCRrs {
127    type Ux = u32;
128}
129///`read()` method returns [`scr::R`](R) reader structure
130impl crate::Readable for SCRrs {}
131///`write(|w| ..)` method takes [`scr::W`](W) writer structure
132impl crate::Writable for SCRrs {
133    type Safety = crate::Unsafe;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
136}
137///`reset()` method sets SCR to value 0
138impl crate::Resettable for SCRrs {
139    const RESET_VALUE: u32 = 0;
140}
stm32g4_staging/stm32g441/tamp/scr.rs

stm32g4_staging/stm32g441/tamp/
scr.rs
