stm32g0xx_hal/rcc/
enable.rs

1use super::*;
2
3macro_rules! bus_enable {
4    ($PER:ident => $en:ident) => {
5        impl Enable for crate::stm32::$PER {
6            #[inline(always)]
7            fn enable(rcc: &mut Rcc) {
8                Self::Bus::enr(rcc).modify(|_, w| w.$en().set_bit());
9            }
10            #[inline(always)]
11            fn disable(rcc: &mut Rcc) {
12                Self::Bus::enr(rcc).modify(|_, w| w.$en().clear_bit());
13            }
14            #[inline(always)]
15            fn is_enabled() -> bool {
16                let rcc = unsafe { &*RCC::ptr() };
17                Self::Bus::enr(rcc).read().$en().bit_is_set()
18            }
19            #[inline(always)]
20            fn is_disabled() -> bool {
21                let rcc = unsafe { &*RCC::ptr() };
22                Self::Bus::enr(rcc).read().$en().bit_is_clear()
23            }
24            #[inline(always)]
25            unsafe fn enable_unchecked() {
26                let rcc = &*RCC::ptr();
27                Self::Bus::enr(rcc).modify(|_, w| w.$en().set_bit());
28            }
29            #[inline(always)]
30            unsafe fn disable_unchecked() {
31                let rcc = &*RCC::ptr();
32                Self::Bus::enr(rcc).modify(|_, w| w.$en().clear_bit());
33            }
34        }
35    };
36}
37macro_rules! bus_smenable {
38    ($PER:ident => $smen:ident) => {
39        impl SMEnable for crate::stm32::$PER {
40            #[inline(always)]
41            fn sleep_mode_enable(rcc: &mut Rcc) {
42                Self::Bus::smenr(rcc).modify(|_, w| w.$smen().set_bit());
43            }
44            #[inline(always)]
45            fn sleep_mode_disable(rcc: &mut Rcc) {
46                Self::Bus::smenr(rcc).modify(|_, w| w.$smen().clear_bit());
47            }
48            #[inline(always)]
49            fn is_sleep_mode_enabled() -> bool {
50                let rcc = unsafe { &*RCC::ptr() };
51                Self::Bus::smenr(rcc).read().$smen().bit_is_set()
52            }
53            #[inline(always)]
54            fn is_sleep_mode_disabled() -> bool {
55                let rcc = unsafe { &*RCC::ptr() };
56                Self::Bus::smenr(rcc).read().$smen().bit_is_clear()
57            }
58            #[inline(always)]
59            unsafe fn sleep_mode_enable_unchecked() {
60                let rcc = &*RCC::ptr();
61                Self::Bus::smenr(rcc).modify(|_, w| w.$smen().set_bit());
62            }
63            #[inline(always)]
64            unsafe fn sleep_mode_disable_unchecked() {
65                let rcc = &*RCC::ptr();
66                Self::Bus::smenr(rcc).modify(|_, w| w.$smen().clear_bit());
67            }
68        }
69    };
70}
71macro_rules! bus_reset {
72    ($PER:ident => $rst:ident) => {
73        impl Reset for crate::stm32::$PER {
74            #[inline(always)]
75            fn reset(rcc: &mut Rcc) {
76                Self::Bus::rstr(rcc).modify(|_, w| w.$rst().set_bit());
77                Self::Bus::rstr(rcc).modify(|_, w| w.$rst().clear_bit());
78            }
79            #[inline(always)]
80            unsafe fn reset_unchecked() {
81                let rcc = &*RCC::ptr();
82                Self::Bus::rstr(rcc).modify(|_, w| w.$rst().set_bit());
83                Self::Bus::rstr(rcc).modify(|_, w| w.$rst().clear_bit());
84            }
85        }
86    };
87}
88
89macro_rules! bus {
90    ($($PER:ident => ($busX:ty, $($en:ident)?, $($smen:ident)?, $($rst:ident)?),)+) => {
91        $(
92            impl crate::Sealed for crate::stm32::$PER {}
93            impl RccBus for crate::stm32::$PER {
94                type Bus = $busX;
95            }
96            $(bus_enable!($PER => $en);)?
97            $(bus_smenable!($PER => $smen);)?
98            $(bus_reset!($PER => $rst);)?
99        )+
100    }
101}
102
103bus! {
104    CRC => (AHB, crcen, crcsmen, crcrst), // 12
105    FLASH => (AHB, flashen, flashsmen, flashrst), // 8
106    DMA => (AHB, dmaen, dmasmen, dmarst), // 0
107
108    DBG => (APB1, dbgen, dbgsmen, dbgrst), // 27
109    I2C1 => (APB1, i2c1en, i2c1smen, i2c1rst), // 21
110    I2C2 => (APB1, i2c2en, i2c2smen, i2c2rst), // 22
111    PWR => (APB1, pwren, pwrsmen, pwrrst), // 28
112
113    SPI2 => (APB1, spi2en, spi2smen, spi2rst), // 14
114    TIM3 => (APB1, tim3en, tim3smen, tim3rst), // 1
115    USART2 => (APB1, usart2en, usart2smen, usart2rst), // 17
116    WWDG => (APB1, wwdgen, wwdgsmen,), // 11
117
118    ADC => (APB2, adcen, adcsmen, adcrst), // 20
119    SPI1 => (APB2, spi1en, spi1smen, spi1rst), // 12
120    TIM1 => (APB2, tim1en, tim1smen, tim1rst), // 11
121    TIM14 => (APB2, tim14en, tim14smen, tim14rst), // 15
122    TIM16 => (APB2, tim16en, tim16smen, tim16rst), // 17
123    TIM17 => (APB2, tim17en, tim17smen, tim17rst), // 18
124    USART1 => (APB2, usart1en, usart1smen, usart1rst), // 14
125
126    GPIOA => (IOP, iopaen, iopasmen, ioparst), // 0
127    GPIOB => (IOP, iopben, iopbsmen, iopbrst), // 1
128    GPIOC => (IOP, iopcen, iopcsmen, iopcrst), // 2
129    GPIOD => (IOP, iopden, iopdsmen, iopdrst), // 3
130    GPIOF => (IOP, iopfen, iopfsmen, iopfrst), // 5
131}
132
133#[cfg(any(feature = "stm32g030", feature = "stm32g031", feature = "stm32g041"))]
134bus! {
135    SYSCFG => (APB2, syscfgen, syscfgsmen, syscfgrst), // 0
136}
137
138#[cfg(any(feature = "stm32g041", feature = "stm32g081"))]
139bus! {
140    AES => (AHB, aesen, aessmen, aesrst), // 16
141    RNG => (AHB, rngen, rngsmen, rngrst), // 18
142}
143
144#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
145bus! {
146    HDMI_CEC => (APB1, cecen, cecsmen, cecrst), // 24
147    DAC => (APB1, dac1en, dac1smen, dac1rst), // 29
148    UCPD1 => (APB1, ucpd1en, ucpd1smen, ucpd1rst), // 25
149    UCPD2 => (APB1, ucpd2en, ucpd2smen, ucpd2rst), // 26
150}
151
152#[cfg(feature = "stm32g0x1")]
153bus! {
154    LPTIM1 => (APB1, lptim1en, lptim1smen, lptim1rst), // 31
155    LPTIM2 => (APB1, lptim2en, lptim2smen, lptim2rst), // 30
156    LPUART => (APB1, lpuart1en, lpuart1smen, lpuart1rst), // 20
157    TIM2 => (APB1, tim2en, tim2smen, tim2rst), // 0
158}
159
160#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
161bus! {
162    TIM6 => (APB1, tim6en, tim6smen, tim6rst), // 4
163    TIM7 => (APB1, tim7en, tim7smen, tim7rst), // 5
164    USART3 => (APB1, usart3en, usart3smen, usart3rst), // 18
165    USART4 => (APB1, usart4en, usart4smen, usart4rst), // 19
166    TIM15 => (APB2, tim15en, tim15smen, tim15rst), // 16
167}
stm32g0xx_hal/rcc/enable.rs

stm32g0xx_hal/rcc/
enable.rs
